[llvm] 866be0a - [RISCV] Pre-commit test for PR56457. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-07-12T11:36:37-07:00
New Revision: 866be0aa8ae40913a9ad999d9b4c525d3f15a129

URL: https://github.com/llvm/llvm-project/commit/866be0aa8ae40913a9ad999d9b4c525d3f15a129
DIFF: https://github.com/llvm/llvm-project/commit/866be0aa8ae40913a9ad999d9b4c525d3f15a129.diff

LOG: [RISCV] Pre-commit test for PR56457. NFC

Added: 
    llvm/test/CodeGen/RISCV/pr56457.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/pr56457.ll b/llvm/test/CodeGen/RISCV/pr56457.ll
new file mode 100644
index 0000000000000..0877dd668f8a7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr56457.ll
@@ -0,0 +1,50 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s
+
+declare i15 @llvm.ctlz.i15(i15, i1)
+
+define i15 @foo(i15 %x) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    slli a1, a0, 49
+; CHECK-NEXT:    srli a2, a1, 49
+; CHECK-NEXT:    beqz a2, .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %cond.false
+; CHECK-NEXT:    srli a1, a1, 50
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    slli a1, a0, 49
+; CHECK-NEXT:    srli a1, a1, 51
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    slli a1, a0, 49
+; CHECK-NEXT:    srli a1, a1, 53
+; CHECK-NEXT:    or a0, a0, a1
+; CHECK-NEXT:    not a0, a0
+; CHECK-NEXT:    slli a0, a0, 49
+; CHECK-NEXT:    srli a0, a0, 49
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECK-NEXT:    ld a1, %lo(.LCPI0_0)(a1)
+; CHECK-NEXT:    lui a2, %hi(.LCPI0_1)
+; CHECK-NEXT:    ld a2, %lo(.LCPI0_1)(a2)
+; CHECK-NEXT:    srli a3, a0, 1
+; CHECK-NEXT:    and a1, a3, a1
+; CHECK-NEXT:    sub a0, a0, a1
+; CHECK-NEXT:    and a1, a0, a2
+; CHECK-NEXT:    srli a0, a0, 2
+; CHECK-NEXT:    and a0, a0, a2
+; CHECK-NEXT:    add a0, a1, a0
+; CHECK-NEXT:    lui a1, %hi(.LCPI0_2)
+; CHECK-NEXT:    ld a1, %lo(.LCPI0_2)(a1)
+; CHECK-NEXT:    lui a2, %hi(.LCPI0_3)
+; CHECK-NEXT:    ld a2, %lo(.LCPI0_3)(a2)
+; CHECK-NEXT:    srli a3, a0, 4
+; CHECK-NEXT:    add a0, a0, a3
+; CHECK-NEXT:    and a0, a0, a1
+; CHECK-NEXT:    mul a0, a0, a2
+; CHECK-NEXT:    srli a0, a0, 56
+; CHECK-NEXT:    ret
+; CHECK-NEXT:  .LBB0_2:
+; CHECK-NEXT:    li a0, 15
+; CHECK-NEXT:    ret
+  %a = call i15 @llvm.ctlz.i15(i15 %x, i1 false)
+  ret i15 %a
+}