[PATCH] D129381: [AMDGPU][CodeGen] Support (register + immediate) SMRD offsets.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev added a comment.

In D129381#3644817 <https://reviews.llvm.org/D129381#3644817>, @foad wrote:

> I don't understand this. I thought AMDGPUResourceUsageAnalysis ran after regalloc so I don't see how it can affect spilling.

You are right, I was too quick thinking that that reduced number of registers is where the higher pressure comes from, sorry for misguiding. Further analysis showed that despite we indeed seem to use less registers in the end, at the register allocation phase an additional spill slot is now introduced due to interference of live ranges and a failure to assign a value to a physical register, which I think is not very surprising as I see lots of moved code in other shaders as well, and for that slot we generate 4 `v_writelane_b32`s and 16 additional `v_readlane_b32`s replacing what previously was 4 `s_mov_b64`s and a `s_waitcnt`. So unfortunately doesn't look like something easy to avoid.


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https://reviews.llvm.org/D129381