[PATCH] D129179: [RISCV] Extend use of SHXADD instructions in RVV spill/reload code.

[Craig Topper via Phabricator via llvm-commits]

craig.topper requested changes to this revision.
craig.topper added inline comments.
This revision now requires changes to proceed.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:1822
+    if (ShiftAmount) {
+      Register ShiftResReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+      BuildMI(MBB, II, DL, get(RISCV::SLLI), ShiftResReg)
----------------
Do we need a new GPR here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129179/new/

https://reviews.llvm.org/D129179