[PATCH] D129375: [AMDGPU] Fix bitcast v4i64/v16i16
Piotr Sobczak via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 8 09:01:59 PDT 2022
piotr added inline comments.
================
Comment at: llvm/test/CodeGen/AMDGPU/bitcast-v4i64-v16i16.ll:30-31
+if.then69.3: ; preds = %if.end76.2
+ %i11 = bitcast <4 x i64> %tmp.sroa.0.1.lcssa to <16 x i16>
+ store <16 x i16> %i11, <16 x i16> addrspace(1)* %out, align 32
+ unreachable
----------------
arsenm wrote:
> Don't you need just this part and the other stores? Why the control flow?
Looks the failing pattern is very sensitive to the IR coming to the isel. I couldn't repro this with only one bitcast either.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D129375/new/
https://reviews.llvm.org/D129375
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