[llvm] 5c45ae4 - [RISCV] Fix wrong register rename for store value during make-compressible optimization

[Kito Cheng via llvm-commits]

Author: Kito Cheng
Date: 2022-07-08T18:07:17+08:00
New Revision: 5c45ae4108d3fdd2a00fbe1890316be82e4fa119

URL: https://github.com/llvm/llvm-project/commit/5c45ae4108d3fdd2a00fbe1890316be82e4fa119
DIFF: https://github.com/llvm/llvm-project/commit/5c45ae4108d3fdd2a00fbe1890316be82e4fa119.diff

LOG: [RISCV] Fix wrong register rename for store value during make-compressible optimization

Current implementation will rename both register in store instructions if
we store base address into memory with same base register, it's OK if
the offset is 0, however that is wrong transform if offset isn't 0, give
a smalle example here:

sd      a0, 808(a0)

We should not transform into:

addi    a2, a0, 768
sd      a2, 40(a2)

That should just rename base address like this:

addi    a2, a0, 768
sd      a0, 40(a2)

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D128876

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
    llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
index 1fc424411c12f..dad0aa4764711 100644
--- a/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
@@ -293,8 +293,16 @@ static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm,
   assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
          "Unsupported instruction for this optimization.");
 
+  int SkipN = 0;
+
+  // Skip the first (value) operand to a store instruction (except if the store
+  // offset is zero) in order to avoid an incorrect transformation.
+  // e.g. sd a0, 808(a0) to addi a2, a0, 768; sd a2, 40(a2)
+  if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
+    SkipN = 1;
+
   // Update registers
-  for (MachineOperand &MO : MI.operands())
+  for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
     if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
       // Do not update operands that define the old register.
       //

diff  --git a/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir b/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
index a913fcb6f6099..e2a0c44d87785 100644
--- a/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
+++ b/llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir
@@ -33,7 +33,7 @@ body:             |
     ; CHECK-NEXT: renamable $x11 = ADDI $x0, 1
     ; CHECK-NEXT: $x12 = ADDI $x10, 768
     ; CHECK-NEXT: SD killed renamable $x11, $x12, 32 :: (store (s64) into %ir.1)
-    ; CHECK-NEXT: SD $x12, $x12, 40 :: (store (s64) into %ir.2)
+    ; CHECK-NEXT: SD renamable $x10, $x12, 40 :: (store (s64) into %ir.2)
     ; CHECK-NEXT: renamable $x11 = ADDI $x0, 2
     ; CHECK-NEXT: SD killed renamable $x11, killed $x12, 48 :: (store (s64) into %ir.3)
     ; CHECK-NEXT: PseudoRET