[llvm] de3b5d7 - [AMDGPU] More GFX11 coverage for tests with generated checks
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 8 03:06:19 PDT 2022
Author: Jay Foad
Date: 2022-07-08T11:06:02+01:00
New Revision: de3b5d73162d372d7bd959e3144600b32df74a62
URL: https://github.com/llvm/llvm-project/commit/de3b5d73162d372d7bd959e3144600b32df74a62
DIFF: https://github.com/llvm/llvm-project/commit/de3b5d73162d372d7bd959e3144600b32df74a62.diff
LOG: [AMDGPU] More GFX11 coverage for tests with generated checks
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
index 07b5608a77e8..4f8ba532db04 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GPRIDX %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=MOVREL %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
; RUN: not --crash llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERR %s
; FIXME: Need constant bus fixup pre-gfx10 for movrel
@@ -27,19 +28,19 @@ define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec,
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s11
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_movreld_b32 s0, s10
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s11
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s10
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i32> %vec, i32 %val, i32 %idx
ret <8 x i32> %insert
@@ -66,19 +67,19 @@ define amdgpu_ps <8 x i8 addrspace(3)*> @dyn_insertelement_v8p3i8_s_s_s(<8 x i8
; GPRIDX-NEXT: s_cselect_b32 s7, s10, s9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8p3i8_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s11
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_movreld_b32 s0, s10
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s11
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s10
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
ret <8 x i8 addrspace(3)*> %insert
@@ -124,45 +125,80 @@ define <8 x float> @dyn_insertelement_v8f32_const_s_v_v(float %val, i32 %idx) {
; GPRIDX-NEXT: v_mov_b32_e32 v1, v9
; GPRIDX-NEXT: s_setpc_b64 s[30:31]
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_const_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_mov_b32 s11, 0x41000000
-; MOVREL-NEXT: s_mov_b32 s4, 1.0
-; MOVREL-NEXT: s_mov_b32 s10, 0x40e00000
-; MOVREL-NEXT: s_mov_b32 s9, 0x40c00000
-; MOVREL-NEXT: s_mov_b32 s8, 0x40a00000
-; MOVREL-NEXT: s_mov_b32 s7, 4.0
-; MOVREL-NEXT: s_mov_b32 s6, 0x40400000
-; MOVREL-NEXT: s_mov_b32 s5, 2.0
-; MOVREL-NEXT: v_mov_b32_e32 v15, s11
-; MOVREL-NEXT: v_mov_b32_e32 v8, s4
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; MOVREL-NEXT: v_mov_b32_e32 v9, s5
-; MOVREL-NEXT: v_mov_b32_e32 v10, s6
-; MOVREL-NEXT: v_mov_b32_e32 v11, s7
-; MOVREL-NEXT: v_mov_b32_e32 v12, s8
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; MOVREL-NEXT: v_mov_b32_e32 v13, s9
-; MOVREL-NEXT: v_mov_b32_e32 v14, s10
-; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
-; MOVREL-NEXT: v_mov_b32_e32 v1, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
-; MOVREL-NEXT: v_mov_b32_e32 v0, v8
-; MOVREL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: dyn_insertelement_v8f32_const_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_mov_b32 s11, 0x41000000
+; GFX10-NEXT: s_mov_b32 s4, 1.0
+; GFX10-NEXT: s_mov_b32 s10, 0x40e00000
+; GFX10-NEXT: s_mov_b32 s9, 0x40c00000
+; GFX10-NEXT: s_mov_b32 s8, 0x40a00000
+; GFX10-NEXT: s_mov_b32 s7, 4.0
+; GFX10-NEXT: s_mov_b32 s6, 0x40400000
+; GFX10-NEXT: s_mov_b32 s5, 2.0
+; GFX10-NEXT: v_mov_b32_e32 v15, s11
+; GFX10-NEXT: v_mov_b32_e32 v8, s4
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-NEXT: v_mov_b32_e32 v9, s5
+; GFX10-NEXT: v_mov_b32_e32 v10, s6
+; GFX10-NEXT: v_mov_b32_e32 v11, s7
+; GFX10-NEXT: v_mov_b32_e32 v12, s8
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_mov_b32_e32 v13, s9
+; GFX10-NEXT: v_mov_b32_e32 v14, s10
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v8
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_const_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_mov_b32 s7, 0x41000000
+; GFX11-NEXT: s_mov_b32 s1, 2.0
+; GFX11-NEXT: s_mov_b32 s0, 1.0
+; GFX11-NEXT: s_mov_b32 s6, 0x40e00000
+; GFX11-NEXT: s_mov_b32 s5, 0x40c00000
+; GFX11-NEXT: s_mov_b32 s4, 0x40a00000
+; GFX11-NEXT: s_mov_b32 s3, 4.0
+; GFX11-NEXT: s_mov_b32 s2, 0x40400000
+; GFX11-NEXT: v_dual_mov_b32 v15, s7 :: v_dual_mov_b32 v14, s6
+; GFX11-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-NEXT: v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
+; GFX11-NEXT: v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v12, s4
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, v9
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v15, v0 :: v_dual_mov_b32 v0, v8
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%insert = insertelement <8 x float> <float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0, float 7.0, float 8.0>, float %val, i32 %idx
ret <8 x float> %insert
@@ -207,42 +243,75 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: v_mov_b32_e32 v15, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; MOVREL-NEXT: v_mov_b32_e32 v9, s1
-; MOVREL-NEXT: v_mov_b32_e32 v10, s2
-; MOVREL-NEXT: v_mov_b32_e32 v11, s3
-; MOVREL-NEXT: v_mov_b32_e32 v12, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
-; MOVREL-NEXT: v_mov_b32_e32 v13, s5
-; MOVREL-NEXT: v_mov_b32_e32 v14, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v9, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v10, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v11, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v12, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v13, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v14, s10, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
-; MOVREL-NEXT: v_mov_b32_e32 v0, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v15, s10, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v8f32_s_s_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: v_mov_b32_e32 v15, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v9, s1
+; GFX10-NEXT: v_mov_b32_e32 v10, s2
+; GFX10-NEXT: v_mov_b32_e32 v11, s3
+; GFX10-NEXT: v_mov_b32_e32 v12, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX10-NEXT: v_mov_b32_e32 v13, s5
+; GFX10-NEXT: v_mov_b32_e32 v14, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v9, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v10, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v11, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v12, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v13, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v14, s10, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, v8
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v15, s10, vcc_lo
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: v_dual_mov_b32 v15, s7 :: v_dual_mov_b32 v14, s6
+; GFX11-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
+; GFX11-NEXT: v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v12, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v9, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v10, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v11, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v12, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v13, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v14, s10, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, v8
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v15, s10, vcc_lo
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -286,28 +355,47 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %v
; GPRIDX-NEXT: v_mov_b32_e32 v0, v8
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: v_mov_b32_e32 v8, v0
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: s_mov_b32 m0, s10
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v8f32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: v_mov_b32_e32 v8, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: s_mov_b32 m0, s10
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_movreld_b32_e32 v0, v8
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: v_mov_b32_e32 v8, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: s_mov_b32 m0, s10
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
+; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
+; GFX11-NEXT: v_movreld_b32_e32 v0, v8
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -335,11 +423,11 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 m0, s3
-; MOVREL-NEXT: v_movreld_b32_e32 v0, s2
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 m0, s3
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, s2
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -384,43 +472,76 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %v
; GPRIDX-NEXT: v_mov_b32_e32 v1, v9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: v_mov_b32_e32 v15, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; MOVREL-NEXT: v_mov_b32_e32 v9, s1
-; MOVREL-NEXT: v_mov_b32_e32 v10, s2
-; MOVREL-NEXT: v_mov_b32_e32 v11, s3
-; MOVREL-NEXT: v_mov_b32_e32 v12, s4
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; MOVREL-NEXT: v_mov_b32_e32 v13, s5
-; MOVREL-NEXT: v_mov_b32_e32 v14, s6
-; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
-; MOVREL-NEXT: v_mov_b32_e32 v1, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
-; MOVREL-NEXT: v_mov_b32_e32 v0, v8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v8f32_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: v_mov_b32_e32 v15, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-NEXT: v_mov_b32_e32 v9, s1
+; GFX10-NEXT: v_mov_b32_e32 v10, s2
+; GFX10-NEXT: v_mov_b32_e32 v11, s3
+; GFX10-NEXT: v_mov_b32_e32 v12, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_mov_b32_e32 v13, s5
+; GFX10-NEXT: v_mov_b32_e32 v14, s6
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, v9
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v15, v0, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v8
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: v_dual_mov_b32 v15, s7 :: v_dual_mov_b32 v14, s6
+; GFX11-NEXT: v_dual_mov_b32 v9, s1 :: v_dual_mov_b32 v8, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-NEXT: v_dual_mov_b32 v11, s3 :: v_dual_mov_b32 v10, s2
+; GFX11-NEXT: v_dual_mov_b32 v13, s5 :: v_dual_mov_b32 v12, s4
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v9, v9, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1
+; GFX11-NEXT: v_mov_b32_e32 v1, v9
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v15, v0 :: v_dual_mov_b32 v0, v8
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -448,25 +569,25 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_v(<8 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_s_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_v:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -493,11 +614,11 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 m0, s2
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -524,11 +645,11 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x i8 addrspace(3
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8p3i8_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 m0, s2
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
%cast.0 = ptrtoint <8 x i8 addrspace(3)*> %insert to <8 x i32>
@@ -557,25 +678,25 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v(<8 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x float> %vec, float %val, i32 %idx
ret <8 x float> %insert
@@ -605,27 +726,27 @@ define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec,
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[18:19]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8i64_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s20
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_movreld_b64 s[0:1], s[18:19]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8i64_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 m0, s20
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i64> %vec, i64 %val, i32 %idx
ret <8 x i64> %insert
@@ -655,27 +776,27 @@ define amdgpu_ps <8 x i8 addrspace(1)*> @dyn_insertelement_v8p1i8_s_s_s(<8 x i8
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[18:19]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8p1i8_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s20
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_movreld_b64 s[0:1], s[18:19]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8p1i8_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 m0, s20
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[18:19]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <8 x i8 addrspace(1)*> %vec, i8 addrspace(1)* %val, i32 %idx
ret <8 x i8 addrspace(1)*> %insert
@@ -748,72 +869,130 @@ define void @dyn_insertelement_v8f64_const_s_v_v(double %val, i32 %idx) {
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_setpc_b64 s[30:31]
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_const_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_mov_b32 s18, 0
-; MOVREL-NEXT: s_mov_b64 s[4:5], 1.0
-; MOVREL-NEXT: s_mov_b32 s19, 0x40200000
-; MOVREL-NEXT: s_mov_b32 s17, 0x401c0000
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s15, 0x40180000
-; MOVREL-NEXT: s_mov_b32 s14, s18
-; MOVREL-NEXT: s_mov_b32 s13, 0x40140000
-; MOVREL-NEXT: s_mov_b32 s12, s18
-; MOVREL-NEXT: s_mov_b64 s[10:11], 4.0
-; MOVREL-NEXT: s_mov_b32 s9, 0x40080000
-; MOVREL-NEXT: s_mov_b32 s8, s18
-; MOVREL-NEXT: s_mov_b64 s[6:7], 2.0
-; MOVREL-NEXT: v_mov_b32_e32 v3, s4
-; MOVREL-NEXT: v_mov_b32_e32 v4, s5
-; MOVREL-NEXT: v_mov_b32_e32 v5, s6
-; MOVREL-NEXT: v_mov_b32_e32 v6, s7
-; MOVREL-NEXT: v_mov_b32_e32 v7, s8
-; MOVREL-NEXT: v_mov_b32_e32 v8, s9
-; MOVREL-NEXT: v_mov_b32_e32 v9, s10
-; MOVREL-NEXT: v_mov_b32_e32 v10, s11
-; MOVREL-NEXT: v_mov_b32_e32 v11, s12
-; MOVREL-NEXT: v_mov_b32_e32 v12, s13
-; MOVREL-NEXT: v_mov_b32_e32 v13, s14
-; MOVREL-NEXT: v_mov_b32_e32 v14, s15
-; MOVREL-NEXT: v_mov_b32_e32 v15, s16
-; MOVREL-NEXT: v_mov_b32_e32 v16, s17
-; MOVREL-NEXT: v_mov_b32_e32 v17, s18
-; MOVREL-NEXT: v_mov_b32_e32 v18, s19
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 1, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s5, 3, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s10, 2, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s6, 4, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s7, 5, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s8, 6, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s9, 7, v2
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, v0, s10
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v0, s5
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v1, s10
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v1, s5
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8
-; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9
-; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8
-; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s9
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: dyn_insertelement_v8f64_const_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_mov_b32 s18, 0
+; GFX10-NEXT: s_mov_b64 s[4:5], 1.0
+; GFX10-NEXT: s_mov_b32 s19, 0x40200000
+; GFX10-NEXT: s_mov_b32 s17, 0x401c0000
+; GFX10-NEXT: s_mov_b32 s16, s18
+; GFX10-NEXT: s_mov_b32 s15, 0x40180000
+; GFX10-NEXT: s_mov_b32 s14, s18
+; GFX10-NEXT: s_mov_b32 s13, 0x40140000
+; GFX10-NEXT: s_mov_b32 s12, s18
+; GFX10-NEXT: s_mov_b64 s[10:11], 4.0
+; GFX10-NEXT: s_mov_b32 s9, 0x40080000
+; GFX10-NEXT: s_mov_b32 s8, s18
+; GFX10-NEXT: s_mov_b64 s[6:7], 2.0
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s5
+; GFX10-NEXT: v_mov_b32_e32 v5, s6
+; GFX10-NEXT: v_mov_b32_e32 v6, s7
+; GFX10-NEXT: v_mov_b32_e32 v7, s8
+; GFX10-NEXT: v_mov_b32_e32 v8, s9
+; GFX10-NEXT: v_mov_b32_e32 v9, s10
+; GFX10-NEXT: v_mov_b32_e32 v10, s11
+; GFX10-NEXT: v_mov_b32_e32 v11, s12
+; GFX10-NEXT: v_mov_b32_e32 v12, s13
+; GFX10-NEXT: v_mov_b32_e32 v13, s14
+; GFX10-NEXT: v_mov_b32_e32 v14, s15
+; GFX10-NEXT: v_mov_b32_e32 v15, s16
+; GFX10-NEXT: v_mov_b32_e32 v16, s17
+; GFX10-NEXT: v_mov_b32_e32 v17, s18
+; GFX10-NEXT: v_mov_b32_e32 v18, s19
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 1, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 3, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s10, 2, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 4, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s7, 5, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s8, 6, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s9, 7, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s10
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s9
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_const_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_mov_b32 s14, 0
+; GFX11-NEXT: s_mov_b32 s15, 0x40200000
+; GFX11-NEXT: s_mov_b32 s13, 0x401c0000
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s11, 0x40180000
+; GFX11-NEXT: s_mov_b32 s10, s14
+; GFX11-NEXT: s_mov_b32 s9, 0x40140000
+; GFX11-NEXT: s_mov_b32 s8, s14
+; GFX11-NEXT: s_mov_b64 s[6:7], 4.0
+; GFX11-NEXT: s_mov_b32 s5, 0x40080000
+; GFX11-NEXT: s_mov_b32 s4, s14
+; GFX11-NEXT: s_mov_b64 s[2:3], 2.0
+; GFX11-NEXT: s_mov_b64 s[0:1], 1.0
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 4, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
+; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
entry:
%insert = insertelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -898,73 +1077,134 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: v_mov_b32_e32 v16, s15
-; MOVREL-NEXT: v_mov_b32_e32 v2, s1
-; MOVREL-NEXT: v_mov_b32_e32 v1, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; MOVREL-NEXT: v_mov_b32_e32 v15, s14
-; MOVREL-NEXT: v_mov_b32_e32 v14, s13
-; MOVREL-NEXT: v_mov_b32_e32 v13, s12
-; MOVREL-NEXT: v_mov_b32_e32 v12, s11
-; MOVREL-NEXT: v_mov_b32_e32 v11, s10
-; MOVREL-NEXT: v_mov_b32_e32 v10, s9
-; MOVREL-NEXT: v_mov_b32_e32 v9, s8
-; MOVREL-NEXT: v_mov_b32_e32 v8, s7
-; MOVREL-NEXT: v_mov_b32_e32 v7, s6
-; MOVREL-NEXT: v_mov_b32_e32 v6, s5
-; MOVREL-NEXT: v_mov_b32_e32 v5, s4
-; MOVREL-NEXT: v_mov_b32_e32 v4, s3
-; MOVREL-NEXT: v_mov_b32_e32 v3, s2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 2, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 4, v0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s2, 5, v0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s3, 6, v0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 7, v0
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, s18, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, s19, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, s18, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, s19, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s18, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s19, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s18, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s19, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s18, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, s19, s4
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[9:12], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[13:16], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_s_s_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: v_mov_b32_e32 v16, s15
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX10-NEXT: v_mov_b32_e32 v15, s14
+; GFX10-NEXT: v_mov_b32_e32 v14, s13
+; GFX10-NEXT: v_mov_b32_e32 v13, s12
+; GFX10-NEXT: v_mov_b32_e32 v12, s11
+; GFX10-NEXT: v_mov_b32_e32 v11, s10
+; GFX10-NEXT: v_mov_b32_e32 v10, s9
+; GFX10-NEXT: v_mov_b32_e32 v9, s8
+; GFX10-NEXT: v_mov_b32_e32 v8, s7
+; GFX10-NEXT: v_mov_b32_e32 v7, s6
+; GFX10-NEXT: v_mov_b32_e32 v6, s5
+; GFX10-NEXT: v_mov_b32_e32 v5, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 4, v0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 5, v0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 6, v0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 7, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s18, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s19, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s18, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s19, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s18, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s19, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s18, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s19, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s18, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s19, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s18, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, s19, s4
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[9:12], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[13:16], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_s_s_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
+; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
+; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
+; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
+; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6
+; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 7, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s18, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s19, s1
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s18, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s19, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s18, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s19, s2
+; GFX11-NEXT: global_store_b128 v[0:1], v[1:4], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[5:8], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[9:12], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[13:16], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1028,52 +1268,92 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: v_mov_b32_e32 v17, s15
-; MOVREL-NEXT: v_mov_b32_e32 v2, s0
-; MOVREL-NEXT: s_lshl_b32 m0, s18, 1
-; MOVREL-NEXT: v_mov_b32_e32 v16, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
-; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
-; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[10:13], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[14:17], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: s_lshl_b32 m0, s18, 1
+; GFX10-NEXT: v_mov_b32_e32 v16, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_movreld_b32_e32 v2, v0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v1
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[10:13], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[14:17], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshl_b32 m0, s18, 1
+; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
+; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_movreld_b32_e32 v2, v0
+; GFX11-NEXT: v_movreld_b32_e32 v3, v1
+; GFX11-NEXT: global_store_b128 v[0:1], v[2:5], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[6:9], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[10:13], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[14:17], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1105,20 +1385,36 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double i
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_lshl_b32 m0, s4, 1
-; MOVREL-NEXT: v_movreld_b32_e32 v0, s2
-; MOVREL-NEXT: v_movreld_b32_e32 v1, s3
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_v_s_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_lshl_b32 m0, s4, 1
+; GFX10-NEXT: v_movreld_b32_e32 v0, s2
+; GFX10-NEXT: v_movreld_b32_e32 v1, s3
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_v_s_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_lshl_b32 m0, s4, 1
+; GFX11-NEXT: v_movreld_b32_e32 v0, s2
+; GFX11-NEXT: v_movreld_b32_e32 v1, s3
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1201,73 +1497,133 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: v_mov_b32_e32 v18, s15
-; MOVREL-NEXT: v_mov_b32_e32 v17, s14
-; MOVREL-NEXT: v_mov_b32_e32 v16, s13
-; MOVREL-NEXT: v_mov_b32_e32 v15, s12
-; MOVREL-NEXT: v_mov_b32_e32 v14, s11
-; MOVREL-NEXT: v_mov_b32_e32 v13, s10
-; MOVREL-NEXT: v_mov_b32_e32 v12, s9
-; MOVREL-NEXT: v_mov_b32_e32 v11, s8
-; MOVREL-NEXT: v_mov_b32_e32 v10, s7
-; MOVREL-NEXT: v_mov_b32_e32 v9, s6
-; MOVREL-NEXT: v_mov_b32_e32 v8, s5
-; MOVREL-NEXT: v_mov_b32_e32 v7, s4
-; MOVREL-NEXT: v_mov_b32_e32 v6, s3
-; MOVREL-NEXT: v_mov_b32_e32 v5, s2
-; MOVREL-NEXT: v_mov_b32_e32 v4, s1
-; MOVREL-NEXT: v_mov_b32_e32 v3, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s6, 2, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, v0, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v1, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
-; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: v_mov_b32_e32 v18, s15
+; GFX10-NEXT: v_mov_b32_e32 v17, s14
+; GFX10-NEXT: v_mov_b32_e32 v16, s13
+; GFX10-NEXT: v_mov_b32_e32 v15, s12
+; GFX10-NEXT: v_mov_b32_e32 v14, s11
+; GFX10-NEXT: v_mov_b32_e32 v13, s10
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
+; GFX10-NEXT: v_mov_b32_e32 v6, s3
+; GFX10-NEXT: v_mov_b32_e32 v5, s2
+; GFX10-NEXT: v_mov_b32_e32 v4, s1
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 3, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 2, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 4, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v0, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v1, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v0, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 4, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v1, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v0, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
+; GFX11-NEXT: global_store_b128 v[0:1], v[3:6], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[7:10], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[11:14], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[15:18], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1320,41 +1676,78 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_v_s_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_v_s_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1386,20 +1779,36 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v16
-; MOVREL-NEXT: v_movreld_b32_e32 v1, v17
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_v_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_lshl_b32 m0, s2, 1
+; GFX10-NEXT: v_movreld_b32_e32 v0, v16
+; GFX10-NEXT: v_movreld_b32_e32 v1, v17
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_v_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_lshl_b32 m0, s2, 1
+; GFX11-NEXT: v_movreld_b32_e32 v0, v16
+; GFX11-NEXT: v_movreld_b32_e32 v1, v17
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1450,41 +1859,77 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v(<8 x double> %vec, double %
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v16 :: v_dual_cndmask_b32 v1, v1, v17
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
@@ -1509,15 +1954,15 @@ define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec,
; GPRIDX-NEXT: s_cselect_b32 s2, s5, s4
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v3i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_cmp_eq_u32 s6, 0
-; MOVREL-NEXT: s_cselect_b32 s0, s5, s2
-; MOVREL-NEXT: s_cmp_eq_u32 s6, 1
-; MOVREL-NEXT: s_cselect_b32 s1, s5, s3
-; MOVREL-NEXT: s_cmp_eq_u32 s6, 2
-; MOVREL-NEXT: s_cselect_b32 s2, s5, s4
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v3i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, s5, s2
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 1
+; GFX10PLUS-NEXT: s_cselect_b32 s1, s5, s3
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s6, 2
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s5, s4
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <3 x i32> %vec, i32 %val, i32 %idx
ret <3 x i32> %insert
@@ -1534,15 +1979,15 @@ define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v3i32_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v3i32_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <3 x float> %vec, float %val, i32 %idx
ret <3 x float> %insert
@@ -1563,19 +2008,19 @@ define amdgpu_ps <5 x i32> @dyn_insertelement_v5i32_s_s_s(<5 x i32> inreg %vec,
; GPRIDX-NEXT: s_cselect_b32 s4, s7, s6
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_cmp_eq_u32 s8, 0
-; MOVREL-NEXT: s_cselect_b32 s0, s7, s2
-; MOVREL-NEXT: s_cmp_eq_u32 s8, 1
-; MOVREL-NEXT: s_cselect_b32 s1, s7, s3
-; MOVREL-NEXT: s_cmp_eq_u32 s8, 2
-; MOVREL-NEXT: s_cselect_b32 s2, s7, s4
-; MOVREL-NEXT: s_cmp_eq_u32 s8, 3
-; MOVREL-NEXT: s_cselect_b32 s3, s7, s5
-; MOVREL-NEXT: s_cmp_eq_u32 s8, 4
-; MOVREL-NEXT: s_cselect_b32 s4, s7, s6
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v5i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, s7, s2
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 1
+; GFX10PLUS-NEXT: s_cselect_b32 s1, s7, s3
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 2
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s7, s4
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 3
+; GFX10PLUS-NEXT: s_cselect_b32 s3, s7, s5
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s8, 4
+; GFX10PLUS-NEXT: s_cselect_b32 s4, s7, s6
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x i32> %vec, i32 %val, i32 %idx
ret <5 x i32> %insert
@@ -1596,19 +2041,19 @@ define amdgpu_ps <5 x float> @dyn_insertelement_v5i32_v_v_s(<5 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5i32_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v5i32_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v5, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x float> %vec, float %val, i32 %idx
ret <5 x float> %insert
@@ -1654,43 +2099,43 @@ define amdgpu_ps <32 x i32> @dyn_insertelement_v32i32_s_s_s(<32 x i32> inreg %ve
; GPRIDX-NEXT: s_movreld_b32 s0, s34
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v32i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s35
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: s_movreld_b32 s0, s34
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v32i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s35
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_mov_b32 s16, s18
+; GFX10PLUS-NEXT: s_mov_b32 s17, s19
+; GFX10PLUS-NEXT: s_mov_b32 s18, s20
+; GFX10PLUS-NEXT: s_mov_b32 s19, s21
+; GFX10PLUS-NEXT: s_mov_b32 s20, s22
+; GFX10PLUS-NEXT: s_mov_b32 s21, s23
+; GFX10PLUS-NEXT: s_mov_b32 s22, s24
+; GFX10PLUS-NEXT: s_mov_b32 s23, s25
+; GFX10PLUS-NEXT: s_mov_b32 s24, s26
+; GFX10PLUS-NEXT: s_mov_b32 s25, s27
+; GFX10PLUS-NEXT: s_mov_b32 s26, s28
+; GFX10PLUS-NEXT: s_mov_b32 s27, s29
+; GFX10PLUS-NEXT: s_mov_b32 s28, s30
+; GFX10PLUS-NEXT: s_mov_b32 s29, s31
+; GFX10PLUS-NEXT: s_mov_b32 s31, s33
+; GFX10PLUS-NEXT: s_mov_b32 s30, s32
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s34
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x i32> %vec, i32 %val, i32 %idx
ret <32 x i32> %insert
@@ -1704,11 +2149,11 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32i32_v_v_s(<32 x float> %vec,
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v32i32_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 m0, s2
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v32
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v32i32_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 m0, s2
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v32
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -1744,27 +2189,45 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> in
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s11
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_movreld_b32 s1, s10
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 m0, s11
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_movreld_b32 s1, s10
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_s_s_s_add_1:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 m0, s11
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_movreld_b32 s1, s10
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -1801,27 +2264,45 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> in
; GPRIDX-NEXT: v_mov_b32_e32 v7, s7
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 m0, s11
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_movreld_b32 s7, s10
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 m0, s11
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_movreld_b32 s7, s10
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v8f32_s_s_s_add_7:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 m0, s11
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_movreld_b32 s7, s10
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -1850,26 +2331,26 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_1(<8 x float> %v
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_add_nc_u32_e32 v9, 1, v9
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v_add_1:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_add_nc_u32_e32 v9, 1, v9
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -1898,26 +2379,26 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_v_add_7(<8 x float> %v
; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_add_nc_u32_e32 v9, 7, v9
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_v_add_7:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_add_nc_u32_e32 v9, 7, v9
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v9
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v7, v7, v8, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%idx.add = add i32 %idx, 7
%insert = insertelement <8 x float> %vec, float %val, i32 %idx.add
@@ -1972,51 +2453,90 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 m0, s20
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_movreld_b64 s[2:3], s[18:19]
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s15
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 m0, s20
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_movreld_b64 s[2:3], s[18:19]
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s15
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 m0, s20
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_movreld_b64 s[2:3], s[18:19]
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
+; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
@@ -2069,42 +2589,80 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_v_add_1(<8 x double> %vec, do
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm
;
-; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_add_nc_u32_e32 v18, 1, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
-; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
-; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
-; MOVREL-NEXT: s_endpgm
+; GFX10-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_add_nc_u32_e32 v18, 1, v18
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
+; GFX10-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
+; GFX10-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_add_nc_u32_e32 v18, 1, v18
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v17, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v18
+; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 6, v18
+; GFX11-NEXT: v_cndmask_b32_e32 v0, v0, v16, vcc_lo
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v16, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, v17, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v16, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v16, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v17, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, v17, s2
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v16, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
+; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
+; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
+; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[8:11], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_store_b128 v[0:1], v[12:15], off dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
entry:
%idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
@@ -2143,27 +2701,27 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_s_s(<16 x i32> inreg %ve
; GPRIDX-NEXT: s_movreld_b32 s0, s18
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s19
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_movreld_b32 s0, s18
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v16i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 m0, s19
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_movreld_b32 s0, s18
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i32> %vec, i32 %val, i32 %idx
ret <16 x i32> %insert
@@ -2209,43 +2767,73 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_s_s(<16 x float> inreg
; GPRIDX-NEXT: v_mov_b32_e32 v15, s15
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16f32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s19
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_movreld_b32 s0, s18
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s15
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v16f32_s_s_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 m0, s19
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_movreld_b32 s0, s18
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s15
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v16f32_s_s_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 m0, s19
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_movreld_b32 s0, s18
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
+; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x float> %vec, float %val, i32 %idx
ret <16 x float> %insert
@@ -2323,75 +2911,129 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_s_s(<32 x float> inreg
; GPRIDX-NEXT: v_mov_b32_e32 v31, s31
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v32f32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 m0, s35
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: s_movreld_b32 s0, s34
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s15
-; MOVREL-NEXT: v_mov_b32_e32 v16, s16
-; MOVREL-NEXT: v_mov_b32_e32 v17, s17
-; MOVREL-NEXT: v_mov_b32_e32 v18, s18
-; MOVREL-NEXT: v_mov_b32_e32 v19, s19
-; MOVREL-NEXT: v_mov_b32_e32 v20, s20
-; MOVREL-NEXT: v_mov_b32_e32 v21, s21
-; MOVREL-NEXT: v_mov_b32_e32 v22, s22
-; MOVREL-NEXT: v_mov_b32_e32 v23, s23
-; MOVREL-NEXT: v_mov_b32_e32 v24, s24
-; MOVREL-NEXT: v_mov_b32_e32 v25, s25
-; MOVREL-NEXT: v_mov_b32_e32 v26, s26
-; MOVREL-NEXT: v_mov_b32_e32 v27, s27
-; MOVREL-NEXT: v_mov_b32_e32 v28, s28
-; MOVREL-NEXT: v_mov_b32_e32 v29, s29
-; MOVREL-NEXT: v_mov_b32_e32 v30, s30
-; MOVREL-NEXT: v_mov_b32_e32 v31, s31
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v32f32_s_s_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 m0, s35
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s16, s18
+; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s18, s20
+; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s20, s22
+; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s22, s24
+; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s24, s26
+; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s26, s28
+; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s28, s30
+; GFX10-NEXT: s_mov_b32 s29, s31
+; GFX10-NEXT: s_mov_b32 s31, s33
+; GFX10-NEXT: s_mov_b32 s30, s32
+; GFX10-NEXT: s_movreld_b32 s0, s34
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s15
+; GFX10-NEXT: v_mov_b32_e32 v16, s16
+; GFX10-NEXT: v_mov_b32_e32 v17, s17
+; GFX10-NEXT: v_mov_b32_e32 v18, s18
+; GFX10-NEXT: v_mov_b32_e32 v19, s19
+; GFX10-NEXT: v_mov_b32_e32 v20, s20
+; GFX10-NEXT: v_mov_b32_e32 v21, s21
+; GFX10-NEXT: v_mov_b32_e32 v22, s22
+; GFX10-NEXT: v_mov_b32_e32 v23, s23
+; GFX10-NEXT: v_mov_b32_e32 v24, s24
+; GFX10-NEXT: v_mov_b32_e32 v25, s25
+; GFX10-NEXT: v_mov_b32_e32 v26, s26
+; GFX10-NEXT: v_mov_b32_e32 v27, s27
+; GFX10-NEXT: v_mov_b32_e32 v28, s28
+; GFX10-NEXT: v_mov_b32_e32 v29, s29
+; GFX10-NEXT: v_mov_b32_e32 v30, s30
+; GFX10-NEXT: v_mov_b32_e32 v31, s31
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v32f32_s_s_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 m0, s35
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s16, s18
+; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s18, s20
+; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s20, s22
+; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s22, s24
+; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s24, s26
+; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s26, s28
+; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s28, s30
+; GFX11-NEXT: s_mov_b32 s29, s31
+; GFX11-NEXT: s_mov_b32 s31, s33
+; GFX11-NEXT: s_mov_b32 s30, s32
+; GFX11-NEXT: s_movreld_b32 s0, s34
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5
+; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7
+; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9
+; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11
+; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13
+; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15
+; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17
+; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
+; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21
+; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23
+; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25
+; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27
+; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29
+; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -2437,43 +3079,43 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_s_s(<16 x i64> inreg %ve
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[34:35]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16i64_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s36
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: s_movreld_b64 s[0:1], s[34:35]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v16i64_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 m0, s36
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_mov_b32 s16, s18
+; GFX10PLUS-NEXT: s_mov_b32 s17, s19
+; GFX10PLUS-NEXT: s_mov_b32 s18, s20
+; GFX10PLUS-NEXT: s_mov_b32 s19, s21
+; GFX10PLUS-NEXT: s_mov_b32 s20, s22
+; GFX10PLUS-NEXT: s_mov_b32 s21, s23
+; GFX10PLUS-NEXT: s_mov_b32 s22, s24
+; GFX10PLUS-NEXT: s_mov_b32 s23, s25
+; GFX10PLUS-NEXT: s_mov_b32 s24, s26
+; GFX10PLUS-NEXT: s_mov_b32 s25, s27
+; GFX10PLUS-NEXT: s_mov_b32 s26, s28
+; GFX10PLUS-NEXT: s_mov_b32 s27, s29
+; GFX10PLUS-NEXT: s_mov_b32 s28, s30
+; GFX10PLUS-NEXT: s_mov_b32 s29, s31
+; GFX10PLUS-NEXT: s_mov_b32 s31, s33
+; GFX10PLUS-NEXT: s_mov_b32 s30, s32
+; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i64> %vec, i64 %val, i32 %idx
ret <16 x i64> %insert
@@ -2519,43 +3161,43 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_s_s(<16 x double> inr
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[34:35]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16f64_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s36
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: s_movreld_b64 s[0:1], s[34:35]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v16f64_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 m0, s36
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_mov_b32 s14, s16
+; GFX10PLUS-NEXT: s_mov_b32 s15, s17
+; GFX10PLUS-NEXT: s_mov_b32 s16, s18
+; GFX10PLUS-NEXT: s_mov_b32 s17, s19
+; GFX10PLUS-NEXT: s_mov_b32 s18, s20
+; GFX10PLUS-NEXT: s_mov_b32 s19, s21
+; GFX10PLUS-NEXT: s_mov_b32 s20, s22
+; GFX10PLUS-NEXT: s_mov_b32 s21, s23
+; GFX10PLUS-NEXT: s_mov_b32 s22, s24
+; GFX10PLUS-NEXT: s_mov_b32 s23, s25
+; GFX10PLUS-NEXT: s_mov_b32 s24, s26
+; GFX10PLUS-NEXT: s_mov_b32 s25, s27
+; GFX10PLUS-NEXT: s_mov_b32 s26, s28
+; GFX10PLUS-NEXT: s_mov_b32 s27, s29
+; GFX10PLUS-NEXT: s_mov_b32 s28, s30
+; GFX10PLUS-NEXT: s_mov_b32 s29, s31
+; GFX10PLUS-NEXT: s_mov_b32 s31, s33
+; GFX10PLUS-NEXT: s_mov_b32 s30, s32
+; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[34:35]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x double> %vec, double %val, i32 %idx
ret <16 x double> %insert
@@ -2617,59 +3259,105 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve
; GPRIDX-NEXT: v_readfirstlane_b32 s15, v16
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16i32_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: v_mov_b32_e32 v16, s15
-; MOVREL-NEXT: v_mov_b32_e32 v1, s0
-; MOVREL-NEXT: s_mov_b32 m0, s18
-; MOVREL-NEXT: v_mov_b32_e32 v15, s14
-; MOVREL-NEXT: v_mov_b32_e32 v14, s13
-; MOVREL-NEXT: v_mov_b32_e32 v13, s12
-; MOVREL-NEXT: v_mov_b32_e32 v12, s11
-; MOVREL-NEXT: v_mov_b32_e32 v11, s10
-; MOVREL-NEXT: v_mov_b32_e32 v10, s9
-; MOVREL-NEXT: v_mov_b32_e32 v9, s8
-; MOVREL-NEXT: v_mov_b32_e32 v8, s7
-; MOVREL-NEXT: v_mov_b32_e32 v7, s6
-; MOVREL-NEXT: v_mov_b32_e32 v6, s5
-; MOVREL-NEXT: v_mov_b32_e32 v5, s4
-; MOVREL-NEXT: v_mov_b32_e32 v4, s3
-; MOVREL-NEXT: v_mov_b32_e32 v3, s2
-; MOVREL-NEXT: v_mov_b32_e32 v2, s1
-; MOVREL-NEXT: v_movreld_b32_e32 v1, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v13
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v14
-; MOVREL-NEXT: v_readfirstlane_b32 s14, v15
-; MOVREL-NEXT: v_readfirstlane_b32 s15, v16
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v16i32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: v_mov_b32_e32 v16, s15
+; GFX10-NEXT: v_mov_b32_e32 v1, s0
+; GFX10-NEXT: s_mov_b32 m0, s18
+; GFX10-NEXT: v_mov_b32_e32 v15, s14
+; GFX10-NEXT: v_mov_b32_e32 v14, s13
+; GFX10-NEXT: v_mov_b32_e32 v13, s12
+; GFX10-NEXT: v_mov_b32_e32 v12, s11
+; GFX10-NEXT: v_mov_b32_e32 v11, s10
+; GFX10-NEXT: v_mov_b32_e32 v10, s9
+; GFX10-NEXT: v_mov_b32_e32 v9, s8
+; GFX10-NEXT: v_mov_b32_e32 v8, s7
+; GFX10-NEXT: v_mov_b32_e32 v7, s6
+; GFX10-NEXT: v_mov_b32_e32 v6, s5
+; GFX10-NEXT: v_mov_b32_e32 v5, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s3
+; GFX10-NEXT: v_mov_b32_e32 v3, s2
+; GFX10-NEXT: v_mov_b32_e32 v2, s1
+; GFX10-NEXT: v_movreld_b32_e32 v1, v0
+; GFX10-NEXT: v_readfirstlane_b32 s0, v1
+; GFX10-NEXT: v_readfirstlane_b32 s1, v2
+; GFX10-NEXT: v_readfirstlane_b32 s2, v3
+; GFX10-NEXT: v_readfirstlane_b32 s3, v4
+; GFX10-NEXT: v_readfirstlane_b32 s4, v5
+; GFX10-NEXT: v_readfirstlane_b32 s5, v6
+; GFX10-NEXT: v_readfirstlane_b32 s6, v7
+; GFX10-NEXT: v_readfirstlane_b32 s7, v8
+; GFX10-NEXT: v_readfirstlane_b32 s8, v9
+; GFX10-NEXT: v_readfirstlane_b32 s9, v10
+; GFX10-NEXT: v_readfirstlane_b32 s10, v11
+; GFX10-NEXT: v_readfirstlane_b32 s11, v12
+; GFX10-NEXT: v_readfirstlane_b32 s12, v13
+; GFX10-NEXT: v_readfirstlane_b32 s13, v14
+; GFX10-NEXT: v_readfirstlane_b32 s14, v15
+; GFX10-NEXT: v_readfirstlane_b32 s15, v16
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v16i32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
+; GFX11-NEXT: s_mov_b32 m0, s18
+; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12
+; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10
+; GFX11-NEXT: v_dual_mov_b32 v10, s9 :: v_dual_mov_b32 v9, s8
+; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v7, s6
+; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4
+; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2
+; GFX11-NEXT: v_movreld_b32_e32 v1, v0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11-NEXT: v_readfirstlane_b32 s1, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v4
+; GFX11-NEXT: v_readfirstlane_b32 s4, v5
+; GFX11-NEXT: v_readfirstlane_b32 s5, v6
+; GFX11-NEXT: v_readfirstlane_b32 s6, v7
+; GFX11-NEXT: v_readfirstlane_b32 s7, v8
+; GFX11-NEXT: v_readfirstlane_b32 s8, v9
+; GFX11-NEXT: v_readfirstlane_b32 s9, v10
+; GFX11-NEXT: v_readfirstlane_b32 s10, v11
+; GFX11-NEXT: v_readfirstlane_b32 s11, v12
+; GFX11-NEXT: v_readfirstlane_b32 s12, v13
+; GFX11-NEXT: v_readfirstlane_b32 s13, v14
+; GFX11-NEXT: v_readfirstlane_b32 s14, v15
+; GFX11-NEXT: v_readfirstlane_b32 s15, v16
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i32> %vec, i32 %val, i32 %idx
ret <16 x i32> %insert
@@ -2716,44 +3404,75 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_v_s(<16 x float> inreg
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16f32_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: v_mov_b32_e32 v16, v0
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: s_mov_b32 m0, s18
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s15
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v16
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v16f32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: v_mov_b32_e32 v16, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: s_mov_b32 m0, s18
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s15
+; GFX10-NEXT: v_movreld_b32_e32 v0, v16
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v16f32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: v_mov_b32_e32 v16, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: s_mov_b32 m0, s18
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
+; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
+; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
+; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
+; GFX11-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v12, s12
+; GFX11-NEXT: v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v14, s14
+; GFX11-NEXT: v_movreld_b32_e32 v0, v16
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x float> %vec, float %val, i32 %idx
ret <16 x float> %insert
@@ -2832,76 +3551,131 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_v_s(<32 x float> inreg
; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v32f32_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: v_mov_b32_e32 v32, v0
-; MOVREL-NEXT: v_mov_b32_e32 v0, s0
-; MOVREL-NEXT: s_mov_b32 m0, s34
-; MOVREL-NEXT: v_mov_b32_e32 v1, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s15
-; MOVREL-NEXT: v_mov_b32_e32 v16, s16
-; MOVREL-NEXT: v_mov_b32_e32 v17, s17
-; MOVREL-NEXT: v_mov_b32_e32 v18, s18
-; MOVREL-NEXT: v_mov_b32_e32 v19, s19
-; MOVREL-NEXT: v_mov_b32_e32 v20, s20
-; MOVREL-NEXT: v_mov_b32_e32 v21, s21
-; MOVREL-NEXT: v_mov_b32_e32 v22, s22
-; MOVREL-NEXT: v_mov_b32_e32 v23, s23
-; MOVREL-NEXT: v_mov_b32_e32 v24, s24
-; MOVREL-NEXT: v_mov_b32_e32 v25, s25
-; MOVREL-NEXT: v_mov_b32_e32 v26, s26
-; MOVREL-NEXT: v_mov_b32_e32 v27, s27
-; MOVREL-NEXT: v_mov_b32_e32 v28, s28
-; MOVREL-NEXT: v_mov_b32_e32 v29, s29
-; MOVREL-NEXT: v_mov_b32_e32 v30, s30
-; MOVREL-NEXT: v_mov_b32_e32 v31, s31
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v32
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v32f32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s16, s18
+; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s18, s20
+; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s20, s22
+; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s22, s24
+; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s24, s26
+; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s26, s28
+; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s28, s30
+; GFX10-NEXT: s_mov_b32 s29, s31
+; GFX10-NEXT: s_mov_b32 s31, s33
+; GFX10-NEXT: s_mov_b32 s30, s32
+; GFX10-NEXT: v_mov_b32_e32 v32, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, s0
+; GFX10-NEXT: s_mov_b32 m0, s34
+; GFX10-NEXT: v_mov_b32_e32 v1, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s15
+; GFX10-NEXT: v_mov_b32_e32 v16, s16
+; GFX10-NEXT: v_mov_b32_e32 v17, s17
+; GFX10-NEXT: v_mov_b32_e32 v18, s18
+; GFX10-NEXT: v_mov_b32_e32 v19, s19
+; GFX10-NEXT: v_mov_b32_e32 v20, s20
+; GFX10-NEXT: v_mov_b32_e32 v21, s21
+; GFX10-NEXT: v_mov_b32_e32 v22, s22
+; GFX10-NEXT: v_mov_b32_e32 v23, s23
+; GFX10-NEXT: v_mov_b32_e32 v24, s24
+; GFX10-NEXT: v_mov_b32_e32 v25, s25
+; GFX10-NEXT: v_mov_b32_e32 v26, s26
+; GFX10-NEXT: v_mov_b32_e32 v27, s27
+; GFX10-NEXT: v_mov_b32_e32 v28, s28
+; GFX10-NEXT: v_mov_b32_e32 v29, s29
+; GFX10-NEXT: v_mov_b32_e32 v30, s30
+; GFX10-NEXT: v_mov_b32_e32 v31, s31
+; GFX10-NEXT: v_movreld_b32_e32 v0, v32
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v32f32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s16, s18
+; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s18, s20
+; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s20, s22
+; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s22, s24
+; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s24, s26
+; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s26, s28
+; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s28, s30
+; GFX11-NEXT: s_mov_b32 s29, s31
+; GFX11-NEXT: s_mov_b32 s31, s33
+; GFX11-NEXT: s_mov_b32 s30, s32
+; GFX11-NEXT: v_mov_b32_e32 v32, v0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3
+; GFX11-NEXT: s_mov_b32 m0, s34
+; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2
+; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v4, s4
+; GFX11-NEXT: v_dual_mov_b32 v7, s7 :: v_dual_mov_b32 v6, s6
+; GFX11-NEXT: v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v8, s8
+; GFX11-NEXT: v_dual_mov_b32 v11, s11 :: v_dual_mov_b32 v10, s10
+; GFX11-NEXT: v_dual_mov_b32 v13, s13 :: v_dual_mov_b32 v12, s12
+; GFX11-NEXT: v_dual_mov_b32 v15, s15 :: v_dual_mov_b32 v14, s14
+; GFX11-NEXT: v_dual_mov_b32 v17, s17 :: v_dual_mov_b32 v16, s16
+; GFX11-NEXT: v_dual_mov_b32 v19, s19 :: v_dual_mov_b32 v18, s18
+; GFX11-NEXT: v_dual_mov_b32 v21, s21 :: v_dual_mov_b32 v20, s20
+; GFX11-NEXT: v_dual_mov_b32 v23, s23 :: v_dual_mov_b32 v22, s22
+; GFX11-NEXT: v_dual_mov_b32 v25, s25 :: v_dual_mov_b32 v24, s24
+; GFX11-NEXT: v_dual_mov_b32 v27, s27 :: v_dual_mov_b32 v26, s26
+; GFX11-NEXT: v_dual_mov_b32 v29, s29 :: v_dual_mov_b32 v28, s28
+; GFX11-NEXT: v_dual_mov_b32 v31, s31 :: v_dual_mov_b32 v30, s30
+; GFX11-NEXT: v_movreld_b32_e32 v0, v32
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <32 x float> %vec, float %val, i32 %idx
ret <32 x float> %insert
@@ -3013,108 +3787,195 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve
; GPRIDX-NEXT: v_readfirstlane_b32 s31, v33
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16i64_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: v_mov_b32_e32 v33, s31
-; MOVREL-NEXT: v_mov_b32_e32 v2, s0
-; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
-; MOVREL-NEXT: v_mov_b32_e32 v32, s30
-; MOVREL-NEXT: v_mov_b32_e32 v31, s29
-; MOVREL-NEXT: v_mov_b32_e32 v30, s28
-; MOVREL-NEXT: v_mov_b32_e32 v29, s27
-; MOVREL-NEXT: v_mov_b32_e32 v28, s26
-; MOVREL-NEXT: v_mov_b32_e32 v27, s25
-; MOVREL-NEXT: v_mov_b32_e32 v26, s24
-; MOVREL-NEXT: v_mov_b32_e32 v25, s23
-; MOVREL-NEXT: v_mov_b32_e32 v24, s22
-; MOVREL-NEXT: v_mov_b32_e32 v23, s21
-; MOVREL-NEXT: v_mov_b32_e32 v22, s20
-; MOVREL-NEXT: v_mov_b32_e32 v21, s19
-; MOVREL-NEXT: v_mov_b32_e32 v20, s18
-; MOVREL-NEXT: v_mov_b32_e32 v19, s17
-; MOVREL-NEXT: v_mov_b32_e32 v18, s16
-; MOVREL-NEXT: v_mov_b32_e32 v17, s15
-; MOVREL-NEXT: v_mov_b32_e32 v16, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
-; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
-; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v13
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v14
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v15
-; MOVREL-NEXT: v_readfirstlane_b32 s14, v16
-; MOVREL-NEXT: v_readfirstlane_b32 s15, v17
-; MOVREL-NEXT: v_readfirstlane_b32 s16, v18
-; MOVREL-NEXT: v_readfirstlane_b32 s17, v19
-; MOVREL-NEXT: v_readfirstlane_b32 s18, v20
-; MOVREL-NEXT: v_readfirstlane_b32 s19, v21
-; MOVREL-NEXT: v_readfirstlane_b32 s20, v22
-; MOVREL-NEXT: v_readfirstlane_b32 s21, v23
-; MOVREL-NEXT: v_readfirstlane_b32 s22, v24
-; MOVREL-NEXT: v_readfirstlane_b32 s23, v25
-; MOVREL-NEXT: v_readfirstlane_b32 s24, v26
-; MOVREL-NEXT: v_readfirstlane_b32 s25, v27
-; MOVREL-NEXT: v_readfirstlane_b32 s26, v28
-; MOVREL-NEXT: v_readfirstlane_b32 s27, v29
-; MOVREL-NEXT: v_readfirstlane_b32 s28, v30
-; MOVREL-NEXT: v_readfirstlane_b32 s29, v31
-; MOVREL-NEXT: v_readfirstlane_b32 s30, v32
-; MOVREL-NEXT: v_readfirstlane_b32 s31, v33
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v16i64_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s29, s31
+; GFX10-NEXT: s_mov_b32 s31, s33
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s16, s18
+; GFX10-NEXT: s_mov_b32 s18, s20
+; GFX10-NEXT: s_mov_b32 s20, s22
+; GFX10-NEXT: s_mov_b32 s22, s24
+; GFX10-NEXT: s_mov_b32 s24, s26
+; GFX10-NEXT: s_mov_b32 s26, s28
+; GFX10-NEXT: s_mov_b32 s28, s30
+; GFX10-NEXT: s_mov_b32 s30, s32
+; GFX10-NEXT: v_mov_b32_e32 v33, s31
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: s_lshl_b32 m0, s34, 1
+; GFX10-NEXT: v_mov_b32_e32 v32, s30
+; GFX10-NEXT: v_mov_b32_e32 v31, s29
+; GFX10-NEXT: v_mov_b32_e32 v30, s28
+; GFX10-NEXT: v_mov_b32_e32 v29, s27
+; GFX10-NEXT: v_mov_b32_e32 v28, s26
+; GFX10-NEXT: v_mov_b32_e32 v27, s25
+; GFX10-NEXT: v_mov_b32_e32 v26, s24
+; GFX10-NEXT: v_mov_b32_e32 v25, s23
+; GFX10-NEXT: v_mov_b32_e32 v24, s22
+; GFX10-NEXT: v_mov_b32_e32 v23, s21
+; GFX10-NEXT: v_mov_b32_e32 v22, s20
+; GFX10-NEXT: v_mov_b32_e32 v21, s19
+; GFX10-NEXT: v_mov_b32_e32 v20, s18
+; GFX10-NEXT: v_mov_b32_e32 v19, s17
+; GFX10-NEXT: v_mov_b32_e32 v18, s16
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: v_mov_b32_e32 v16, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_movreld_b32_e32 v2, v0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: v_readfirstlane_b32 s1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s2, v4
+; GFX10-NEXT: v_readfirstlane_b32 s3, v5
+; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_readfirstlane_b32 s5, v7
+; GFX10-NEXT: v_readfirstlane_b32 s6, v8
+; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s8, v10
+; GFX10-NEXT: v_readfirstlane_b32 s9, v11
+; GFX10-NEXT: v_readfirstlane_b32 s10, v12
+; GFX10-NEXT: v_readfirstlane_b32 s11, v13
+; GFX10-NEXT: v_readfirstlane_b32 s12, v14
+; GFX10-NEXT: v_readfirstlane_b32 s13, v15
+; GFX10-NEXT: v_readfirstlane_b32 s14, v16
+; GFX10-NEXT: v_readfirstlane_b32 s15, v17
+; GFX10-NEXT: v_readfirstlane_b32 s16, v18
+; GFX10-NEXT: v_readfirstlane_b32 s17, v19
+; GFX10-NEXT: v_readfirstlane_b32 s18, v20
+; GFX10-NEXT: v_readfirstlane_b32 s19, v21
+; GFX10-NEXT: v_readfirstlane_b32 s20, v22
+; GFX10-NEXT: v_readfirstlane_b32 s21, v23
+; GFX10-NEXT: v_readfirstlane_b32 s22, v24
+; GFX10-NEXT: v_readfirstlane_b32 s23, v25
+; GFX10-NEXT: v_readfirstlane_b32 s24, v26
+; GFX10-NEXT: v_readfirstlane_b32 s25, v27
+; GFX10-NEXT: v_readfirstlane_b32 s26, v28
+; GFX10-NEXT: v_readfirstlane_b32 s27, v29
+; GFX10-NEXT: v_readfirstlane_b32 s28, v30
+; GFX10-NEXT: v_readfirstlane_b32 s29, v31
+; GFX10-NEXT: v_readfirstlane_b32 s30, v32
+; GFX10-NEXT: v_readfirstlane_b32 s31, v33
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v16i64_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s29, s31
+; GFX11-NEXT: s_mov_b32 s31, s33
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s16, s18
+; GFX11-NEXT: s_mov_b32 s18, s20
+; GFX11-NEXT: s_mov_b32 s20, s22
+; GFX11-NEXT: s_mov_b32 s22, s24
+; GFX11-NEXT: s_mov_b32 s24, s26
+; GFX11-NEXT: s_mov_b32 s26, s28
+; GFX11-NEXT: s_mov_b32 s28, s30
+; GFX11-NEXT: s_mov_b32 s30, s32
+; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshl_b32 m0, s34, 1
+; GFX11-NEXT: v_dual_mov_b32 v31, s29 :: v_dual_mov_b32 v30, s28
+; GFX11-NEXT: v_dual_mov_b32 v29, s27 :: v_dual_mov_b32 v28, s26
+; GFX11-NEXT: v_dual_mov_b32 v27, s25 :: v_dual_mov_b32 v26, s24
+; GFX11-NEXT: v_dual_mov_b32 v25, s23 :: v_dual_mov_b32 v24, s22
+; GFX11-NEXT: v_dual_mov_b32 v23, s21 :: v_dual_mov_b32 v22, s20
+; GFX11-NEXT: v_dual_mov_b32 v21, s19 :: v_dual_mov_b32 v20, s18
+; GFX11-NEXT: v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v18, s16
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
+; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_movreld_b32_e32 v2, v0
+; GFX11-NEXT: v_movreld_b32_e32 v3, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: v_readfirstlane_b32 s4, v6
+; GFX11-NEXT: v_readfirstlane_b32 s5, v7
+; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-NEXT: v_readfirstlane_b32 s9, v11
+; GFX11-NEXT: v_readfirstlane_b32 s10, v12
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s12, v14
+; GFX11-NEXT: v_readfirstlane_b32 s13, v15
+; GFX11-NEXT: v_readfirstlane_b32 s14, v16
+; GFX11-NEXT: v_readfirstlane_b32 s15, v17
+; GFX11-NEXT: v_readfirstlane_b32 s16, v18
+; GFX11-NEXT: v_readfirstlane_b32 s17, v19
+; GFX11-NEXT: v_readfirstlane_b32 s18, v20
+; GFX11-NEXT: v_readfirstlane_b32 s19, v21
+; GFX11-NEXT: v_readfirstlane_b32 s20, v22
+; GFX11-NEXT: v_readfirstlane_b32 s21, v23
+; GFX11-NEXT: v_readfirstlane_b32 s22, v24
+; GFX11-NEXT: v_readfirstlane_b32 s23, v25
+; GFX11-NEXT: v_readfirstlane_b32 s24, v26
+; GFX11-NEXT: v_readfirstlane_b32 s25, v27
+; GFX11-NEXT: v_readfirstlane_b32 s26, v28
+; GFX11-NEXT: v_readfirstlane_b32 s27, v29
+; GFX11-NEXT: v_readfirstlane_b32 s28, v30
+; GFX11-NEXT: v_readfirstlane_b32 s29, v31
+; GFX11-NEXT: v_readfirstlane_b32 s30, v32
+; GFX11-NEXT: v_readfirstlane_b32 s31, v33
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x i64> %vec, i64 %val, i32 %idx
ret <16 x i64> %insert
@@ -3226,108 +4087,195 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr
; GPRIDX-NEXT: v_readfirstlane_b32 s31, v33
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v16f64_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_mov_b32 s15, s17
-; MOVREL-NEXT: s_mov_b32 s17, s19
-; MOVREL-NEXT: s_mov_b32 s19, s21
-; MOVREL-NEXT: s_mov_b32 s21, s23
-; MOVREL-NEXT: s_mov_b32 s23, s25
-; MOVREL-NEXT: s_mov_b32 s25, s27
-; MOVREL-NEXT: s_mov_b32 s27, s29
-; MOVREL-NEXT: s_mov_b32 s29, s31
-; MOVREL-NEXT: s_mov_b32 s31, s33
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s14, s16
-; MOVREL-NEXT: s_mov_b32 s16, s18
-; MOVREL-NEXT: s_mov_b32 s18, s20
-; MOVREL-NEXT: s_mov_b32 s20, s22
-; MOVREL-NEXT: s_mov_b32 s22, s24
-; MOVREL-NEXT: s_mov_b32 s24, s26
-; MOVREL-NEXT: s_mov_b32 s26, s28
-; MOVREL-NEXT: s_mov_b32 s28, s30
-; MOVREL-NEXT: s_mov_b32 s30, s32
-; MOVREL-NEXT: v_mov_b32_e32 v33, s31
-; MOVREL-NEXT: v_mov_b32_e32 v2, s0
-; MOVREL-NEXT: s_lshl_b32 m0, s34, 1
-; MOVREL-NEXT: v_mov_b32_e32 v32, s30
-; MOVREL-NEXT: v_mov_b32_e32 v31, s29
-; MOVREL-NEXT: v_mov_b32_e32 v30, s28
-; MOVREL-NEXT: v_mov_b32_e32 v29, s27
-; MOVREL-NEXT: v_mov_b32_e32 v28, s26
-; MOVREL-NEXT: v_mov_b32_e32 v27, s25
-; MOVREL-NEXT: v_mov_b32_e32 v26, s24
-; MOVREL-NEXT: v_mov_b32_e32 v25, s23
-; MOVREL-NEXT: v_mov_b32_e32 v24, s22
-; MOVREL-NEXT: v_mov_b32_e32 v23, s21
-; MOVREL-NEXT: v_mov_b32_e32 v22, s20
-; MOVREL-NEXT: v_mov_b32_e32 v21, s19
-; MOVREL-NEXT: v_mov_b32_e32 v20, s18
-; MOVREL-NEXT: v_mov_b32_e32 v19, s17
-; MOVREL-NEXT: v_mov_b32_e32 v18, s16
-; MOVREL-NEXT: v_mov_b32_e32 v17, s15
-; MOVREL-NEXT: v_mov_b32_e32 v16, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
-; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
-; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v13
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v14
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v15
-; MOVREL-NEXT: v_readfirstlane_b32 s14, v16
-; MOVREL-NEXT: v_readfirstlane_b32 s15, v17
-; MOVREL-NEXT: v_readfirstlane_b32 s16, v18
-; MOVREL-NEXT: v_readfirstlane_b32 s17, v19
-; MOVREL-NEXT: v_readfirstlane_b32 s18, v20
-; MOVREL-NEXT: v_readfirstlane_b32 s19, v21
-; MOVREL-NEXT: v_readfirstlane_b32 s20, v22
-; MOVREL-NEXT: v_readfirstlane_b32 s21, v23
-; MOVREL-NEXT: v_readfirstlane_b32 s22, v24
-; MOVREL-NEXT: v_readfirstlane_b32 s23, v25
-; MOVREL-NEXT: v_readfirstlane_b32 s24, v26
-; MOVREL-NEXT: v_readfirstlane_b32 s25, v27
-; MOVREL-NEXT: v_readfirstlane_b32 s26, v28
-; MOVREL-NEXT: v_readfirstlane_b32 s27, v29
-; MOVREL-NEXT: v_readfirstlane_b32 s28, v30
-; MOVREL-NEXT: v_readfirstlane_b32 s29, v31
-; MOVREL-NEXT: v_readfirstlane_b32 s30, v32
-; MOVREL-NEXT: v_readfirstlane_b32 s31, v33
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v16f64_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: s_mov_b32 s15, s17
+; GFX10-NEXT: s_mov_b32 s17, s19
+; GFX10-NEXT: s_mov_b32 s19, s21
+; GFX10-NEXT: s_mov_b32 s21, s23
+; GFX10-NEXT: s_mov_b32 s23, s25
+; GFX10-NEXT: s_mov_b32 s25, s27
+; GFX10-NEXT: s_mov_b32 s27, s29
+; GFX10-NEXT: s_mov_b32 s29, s31
+; GFX10-NEXT: s_mov_b32 s31, s33
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s14, s16
+; GFX10-NEXT: s_mov_b32 s16, s18
+; GFX10-NEXT: s_mov_b32 s18, s20
+; GFX10-NEXT: s_mov_b32 s20, s22
+; GFX10-NEXT: s_mov_b32 s22, s24
+; GFX10-NEXT: s_mov_b32 s24, s26
+; GFX10-NEXT: s_mov_b32 s26, s28
+; GFX10-NEXT: s_mov_b32 s28, s30
+; GFX10-NEXT: s_mov_b32 s30, s32
+; GFX10-NEXT: v_mov_b32_e32 v33, s31
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: s_lshl_b32 m0, s34, 1
+; GFX10-NEXT: v_mov_b32_e32 v32, s30
+; GFX10-NEXT: v_mov_b32_e32 v31, s29
+; GFX10-NEXT: v_mov_b32_e32 v30, s28
+; GFX10-NEXT: v_mov_b32_e32 v29, s27
+; GFX10-NEXT: v_mov_b32_e32 v28, s26
+; GFX10-NEXT: v_mov_b32_e32 v27, s25
+; GFX10-NEXT: v_mov_b32_e32 v26, s24
+; GFX10-NEXT: v_mov_b32_e32 v25, s23
+; GFX10-NEXT: v_mov_b32_e32 v24, s22
+; GFX10-NEXT: v_mov_b32_e32 v23, s21
+; GFX10-NEXT: v_mov_b32_e32 v22, s20
+; GFX10-NEXT: v_mov_b32_e32 v21, s19
+; GFX10-NEXT: v_mov_b32_e32 v20, s18
+; GFX10-NEXT: v_mov_b32_e32 v19, s17
+; GFX10-NEXT: v_mov_b32_e32 v18, s16
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: v_mov_b32_e32 v16, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_movreld_b32_e32 v2, v0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: v_readfirstlane_b32 s1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s2, v4
+; GFX10-NEXT: v_readfirstlane_b32 s3, v5
+; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_readfirstlane_b32 s5, v7
+; GFX10-NEXT: v_readfirstlane_b32 s6, v8
+; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s8, v10
+; GFX10-NEXT: v_readfirstlane_b32 s9, v11
+; GFX10-NEXT: v_readfirstlane_b32 s10, v12
+; GFX10-NEXT: v_readfirstlane_b32 s11, v13
+; GFX10-NEXT: v_readfirstlane_b32 s12, v14
+; GFX10-NEXT: v_readfirstlane_b32 s13, v15
+; GFX10-NEXT: v_readfirstlane_b32 s14, v16
+; GFX10-NEXT: v_readfirstlane_b32 s15, v17
+; GFX10-NEXT: v_readfirstlane_b32 s16, v18
+; GFX10-NEXT: v_readfirstlane_b32 s17, v19
+; GFX10-NEXT: v_readfirstlane_b32 s18, v20
+; GFX10-NEXT: v_readfirstlane_b32 s19, v21
+; GFX10-NEXT: v_readfirstlane_b32 s20, v22
+; GFX10-NEXT: v_readfirstlane_b32 s21, v23
+; GFX10-NEXT: v_readfirstlane_b32 s22, v24
+; GFX10-NEXT: v_readfirstlane_b32 s23, v25
+; GFX10-NEXT: v_readfirstlane_b32 s24, v26
+; GFX10-NEXT: v_readfirstlane_b32 s25, v27
+; GFX10-NEXT: v_readfirstlane_b32 s26, v28
+; GFX10-NEXT: v_readfirstlane_b32 s27, v29
+; GFX10-NEXT: v_readfirstlane_b32 s28, v30
+; GFX10-NEXT: v_readfirstlane_b32 s29, v31
+; GFX10-NEXT: v_readfirstlane_b32 s30, v32
+; GFX10-NEXT: v_readfirstlane_b32 s31, v33
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v16f64_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: s_mov_b32 s15, s17
+; GFX11-NEXT: s_mov_b32 s17, s19
+; GFX11-NEXT: s_mov_b32 s19, s21
+; GFX11-NEXT: s_mov_b32 s21, s23
+; GFX11-NEXT: s_mov_b32 s23, s25
+; GFX11-NEXT: s_mov_b32 s25, s27
+; GFX11-NEXT: s_mov_b32 s27, s29
+; GFX11-NEXT: s_mov_b32 s29, s31
+; GFX11-NEXT: s_mov_b32 s31, s33
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s14, s16
+; GFX11-NEXT: s_mov_b32 s16, s18
+; GFX11-NEXT: s_mov_b32 s18, s20
+; GFX11-NEXT: s_mov_b32 s20, s22
+; GFX11-NEXT: s_mov_b32 s22, s24
+; GFX11-NEXT: s_mov_b32 s24, s26
+; GFX11-NEXT: s_mov_b32 s26, s28
+; GFX11-NEXT: s_mov_b32 s28, s30
+; GFX11-NEXT: s_mov_b32 s30, s32
+; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshl_b32 m0, s34, 1
+; GFX11-NEXT: v_dual_mov_b32 v31, s29 :: v_dual_mov_b32 v30, s28
+; GFX11-NEXT: v_dual_mov_b32 v29, s27 :: v_dual_mov_b32 v28, s26
+; GFX11-NEXT: v_dual_mov_b32 v27, s25 :: v_dual_mov_b32 v26, s24
+; GFX11-NEXT: v_dual_mov_b32 v25, s23 :: v_dual_mov_b32 v24, s22
+; GFX11-NEXT: v_dual_mov_b32 v23, s21 :: v_dual_mov_b32 v22, s20
+; GFX11-NEXT: v_dual_mov_b32 v21, s19 :: v_dual_mov_b32 v20, s18
+; GFX11-NEXT: v_dual_mov_b32 v19, s17 :: v_dual_mov_b32 v18, s16
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
+; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_movreld_b32_e32 v2, v0
+; GFX11-NEXT: v_movreld_b32_e32 v3, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: v_readfirstlane_b32 s4, v6
+; GFX11-NEXT: v_readfirstlane_b32 s5, v7
+; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-NEXT: v_readfirstlane_b32 s9, v11
+; GFX11-NEXT: v_readfirstlane_b32 s10, v12
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s12, v14
+; GFX11-NEXT: v_readfirstlane_b32 s13, v15
+; GFX11-NEXT: v_readfirstlane_b32 s14, v16
+; GFX11-NEXT: v_readfirstlane_b32 s15, v17
+; GFX11-NEXT: v_readfirstlane_b32 s16, v18
+; GFX11-NEXT: v_readfirstlane_b32 s17, v19
+; GFX11-NEXT: v_readfirstlane_b32 s18, v20
+; GFX11-NEXT: v_readfirstlane_b32 s19, v21
+; GFX11-NEXT: v_readfirstlane_b32 s20, v22
+; GFX11-NEXT: v_readfirstlane_b32 s21, v23
+; GFX11-NEXT: v_readfirstlane_b32 s22, v24
+; GFX11-NEXT: v_readfirstlane_b32 s23, v25
+; GFX11-NEXT: v_readfirstlane_b32 s24, v26
+; GFX11-NEXT: v_readfirstlane_b32 s25, v27
+; GFX11-NEXT: v_readfirstlane_b32 s26, v28
+; GFX11-NEXT: v_readfirstlane_b32 s27, v29
+; GFX11-NEXT: v_readfirstlane_b32 s28, v30
+; GFX11-NEXT: v_readfirstlane_b32 s29, v31
+; GFX11-NEXT: v_readfirstlane_b32 s30, v32
+; GFX11-NEXT: v_readfirstlane_b32 s31, v33
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <16 x double> %vec, double %val, i32 %idx
ret <16 x double> %insert
@@ -3352,23 +4300,23 @@ define amdgpu_ps <7 x i32> @dyn_insertelement_v7i32_s_s_s(<7 x i32> inreg %vec,
; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7i32_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 0
-; MOVREL-NEXT: s_cselect_b32 s0, s9, s2
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 1
-; MOVREL-NEXT: s_cselect_b32 s1, s9, s3
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 2
-; MOVREL-NEXT: s_cselect_b32 s2, s9, s4
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 3
-; MOVREL-NEXT: s_cselect_b32 s3, s9, s5
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 4
-; MOVREL-NEXT: s_cselect_b32 s4, s9, s6
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 5
-; MOVREL-NEXT: s_cselect_b32 s5, s9, s7
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 6
-; MOVREL-NEXT: s_cselect_b32 s6, s9, s8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7i32_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, s9, s2
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 1
+; GFX10PLUS-NEXT: s_cselect_b32 s1, s9, s3
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 2
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s9, s4
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 3
+; GFX10PLUS-NEXT: s_cselect_b32 s3, s9, s5
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 4
+; GFX10PLUS-NEXT: s_cselect_b32 s4, s9, s6
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 5
+; GFX10PLUS-NEXT: s_cselect_b32 s5, s9, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 6
+; GFX10PLUS-NEXT: s_cselect_b32 s6, s9, s8
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x i32> %vec, i32 %val, i32 %idx
ret <7 x i32> %insert
@@ -3393,23 +4341,23 @@ define amdgpu_ps <7 x i8 addrspace(3)*> @dyn_insertelement_v7p3i8_s_s_s(<7 x i8
; GPRIDX-NEXT: s_cselect_b32 s6, s9, s8
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7p3i8_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 0
-; MOVREL-NEXT: s_cselect_b32 s0, s9, s2
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 1
-; MOVREL-NEXT: s_cselect_b32 s1, s9, s3
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 2
-; MOVREL-NEXT: s_cselect_b32 s2, s9, s4
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 3
-; MOVREL-NEXT: s_cselect_b32 s3, s9, s5
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 4
-; MOVREL-NEXT: s_cselect_b32 s4, s9, s6
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 5
-; MOVREL-NEXT: s_cselect_b32 s5, s9, s7
-; MOVREL-NEXT: s_cmp_eq_u32 s10, 6
-; MOVREL-NEXT: s_cselect_b32 s6, s9, s8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7p3i8_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 0
+; GFX10PLUS-NEXT: s_cselect_b32 s0, s9, s2
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 1
+; GFX10PLUS-NEXT: s_cselect_b32 s1, s9, s3
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 2
+; GFX10PLUS-NEXT: s_cselect_b32 s2, s9, s4
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 3
+; GFX10PLUS-NEXT: s_cselect_b32 s3, s9, s5
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 4
+; GFX10PLUS-NEXT: s_cselect_b32 s4, s9, s6
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 5
+; GFX10PLUS-NEXT: s_cselect_b32 s5, s9, s7
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s10, 6
+; GFX10PLUS-NEXT: s_cselect_b32 s6, s9, s8
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x i8 addrspace(3)*> %vec, i8 addrspace(3)* %val, i32 %idx
ret <7 x i8 addrspace(3)*> %insert
@@ -3449,38 +4397,68 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_s(<7 x float> inreg %v
; GPRIDX-NEXT: v_mov_b32_e32 v0, v7
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: v_mov_b32_e32 v13, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 0
-; MOVREL-NEXT: v_mov_b32_e32 v8, s1
-; MOVREL-NEXT: v_mov_b32_e32 v9, s2
-; MOVREL-NEXT: v_mov_b32_e32 v10, s3
-; MOVREL-NEXT: v_mov_b32_e32 v11, s4
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1
-; MOVREL-NEXT: v_mov_b32_e32 v12, s5
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 2
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v9, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 3
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v10, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 4
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v11, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 5
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v12, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 6
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v13, v0, vcc_lo
-; MOVREL-NEXT: v_mov_b32_e32 v0, v7
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f32_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: v_mov_b32_e32 v13, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 0
+; GFX10-NEXT: v_mov_b32_e32 v8, s1
+; GFX10-NEXT: v_mov_b32_e32 v9, s2
+; GFX10-NEXT: v_mov_b32_e32 v10, s3
+; GFX10-NEXT: v_mov_b32_e32 v11, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1
+; GFX10-NEXT: v_mov_b32_e32 v12, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 2
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v9, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 3
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v10, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 4
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v11, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 5
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v12, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 6
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v13, v0, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v7
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f32_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: v_dual_mov_b32 v13, s6 :: v_dual_mov_b32 v12, s5
+; GFX11-NEXT: v_dual_mov_b32 v9, s2 :: v_dual_mov_b32 v8, s1
+; GFX11-NEXT: v_mov_b32_e32 v7, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 0
+; GFX11-NEXT: v_dual_mov_b32 v11, s4 :: v_dual_mov_b32 v10, s3
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 1
+; GFX11-NEXT: v_cndmask_b32_e32 v1, v8, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 2
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v9, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 3
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v10, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 4
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v11, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 5
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v12, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s9, 6
+; GFX11-NEXT: v_cndmask_b32_e32 v6, v13, v0, vcc_lo
+; GFX11-NEXT: v_mov_b32_e32 v0, v7
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -3521,39 +4499,69 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %v
; GPRIDX-NEXT: v_mov_b32_e32 v1, v7
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f32_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: v_mov_b32_e32 v14, s6
-; MOVREL-NEXT: v_mov_b32_e32 v8, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; MOVREL-NEXT: v_mov_b32_e32 v9, s1
-; MOVREL-NEXT: v_mov_b32_e32 v10, s2
-; MOVREL-NEXT: v_mov_b32_e32 v11, s3
-; MOVREL-NEXT: v_mov_b32_e32 v12, s4
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
-; MOVREL-NEXT: v_mov_b32_e32 v13, s5
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
-; MOVREL-NEXT: v_mov_b32_e32 v1, v7
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
-; MOVREL-NEXT: v_mov_b32_e32 v0, v8
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f32_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: v_mov_b32_e32 v14, s6
+; GFX10-NEXT: v_mov_b32_e32 v8, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX10-NEXT: v_mov_b32_e32 v9, s1
+; GFX10-NEXT: v_mov_b32_e32 v10, s2
+; GFX10-NEXT: v_mov_b32_e32 v11, s3
+; GFX10-NEXT: v_mov_b32_e32 v12, s4
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX10-NEXT: v_mov_b32_e32 v13, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX10-NEXT: v_mov_b32_e32 v1, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v14, v0, vcc_lo
+; GFX10-NEXT: v_mov_b32_e32 v0, v8
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f32_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: v_dual_mov_b32 v14, s6 :: v_dual_mov_b32 v13, s5
+; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v9, s1
+; GFX11-NEXT: v_mov_b32_e32 v8, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX11-NEXT: v_dual_mov_b32 v12, s4 :: v_dual_mov_b32 v11, s3
+; GFX11-NEXT: v_cndmask_b32_e32 v8, v8, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v7, v9, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v2, v10, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v3, v11, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v4, v12, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1
+; GFX11-NEXT: v_cndmask_b32_e32 v5, v13, v0, vcc_lo
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1
+; GFX11-NEXT: v_dual_mov_b32 v1, v7 :: v_dual_cndmask_b32 v6, v14, v0
+; GFX11-NEXT: v_mov_b32_e32 v0, v8
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -3578,23 +4586,23 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_s(<7 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 5
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 6
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7f32_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 5
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 6
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -3619,23 +4627,23 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_v(<7 x float> %vec, fl
; GPRIDX-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f32_v_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7f32_v_v_v:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v3, v3, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8
+; GFX10PLUS-NEXT: v_cndmask_b32_e32 v6, v6, v7, vcc_lo
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x float> %vec, float %val, i32 %idx
ret <7 x float> %insert
@@ -3663,25 +4671,25 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg
; GPRIDX-NEXT: s_movreld_b64 s[0:1], s[16:17]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f64_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 m0, s18
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: s_movreld_b64 s[0:1], s[16:17]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7f64_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_mov_b32 s0, s2
+; GFX10PLUS-NEXT: s_mov_b32 s1, s3
+; GFX10PLUS-NEXT: s_mov_b32 m0, s18
+; GFX10PLUS-NEXT: s_mov_b32 s2, s4
+; GFX10PLUS-NEXT: s_mov_b32 s3, s5
+; GFX10PLUS-NEXT: s_mov_b32 s4, s6
+; GFX10PLUS-NEXT: s_mov_b32 s5, s7
+; GFX10PLUS-NEXT: s_mov_b32 s6, s8
+; GFX10PLUS-NEXT: s_mov_b32 s7, s9
+; GFX10PLUS-NEXT: s_mov_b32 s8, s10
+; GFX10PLUS-NEXT: s_mov_b32 s9, s11
+; GFX10PLUS-NEXT: s_mov_b32 s10, s12
+; GFX10PLUS-NEXT: s_mov_b32 s11, s13
+; GFX10PLUS-NEXT: s_mov_b32 s12, s14
+; GFX10PLUS-NEXT: s_mov_b32 s13, s15
+; GFX10PLUS-NEXT: s_movreld_b64 s[0:1], s[16:17]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -3741,56 +4749,99 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v15
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f64_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: v_mov_b32_e32 v17, s15
-; MOVREL-NEXT: v_mov_b32_e32 v2, s0
-; MOVREL-NEXT: s_lshl_b32 m0, s16, 1
-; MOVREL-NEXT: v_mov_b32_e32 v16, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
-; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
-; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v13
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v14
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v15
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f64_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: s_lshl_b32 m0, s16, 1
+; GFX10-NEXT: v_mov_b32_e32 v16, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_movreld_b32_e32 v2, v0
+; GFX10-NEXT: v_movreld_b32_e32 v3, v1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: v_readfirstlane_b32 s1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s2, v4
+; GFX10-NEXT: v_readfirstlane_b32 s3, v5
+; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_readfirstlane_b32 s5, v7
+; GFX10-NEXT: v_readfirstlane_b32 s6, v8
+; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s8, v10
+; GFX10-NEXT: v_readfirstlane_b32 s9, v11
+; GFX10-NEXT: v_readfirstlane_b32 s10, v12
+; GFX10-NEXT: v_readfirstlane_b32 s11, v13
+; GFX10-NEXT: v_readfirstlane_b32 s12, v14
+; GFX10-NEXT: v_readfirstlane_b32 s13, v15
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f64_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: s_lshl_b32 m0, s16, 1
+; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
+; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_movreld_b32_e32 v2, v0
+; GFX11-NEXT: v_movreld_b32_e32 v3, v1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: v_readfirstlane_b32 s4, v6
+; GFX11-NEXT: v_readfirstlane_b32 s5, v7
+; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s8, v10
+; GFX11-NEXT: v_readfirstlane_b32 s9, v11
+; GFX11-NEXT: v_readfirstlane_b32 s10, v12
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s12, v14
+; GFX11-NEXT: v_readfirstlane_b32 s13, v15
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -3866,74 +4917,132 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v1
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f64_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: s_mov_b32 s10, s12
-; MOVREL-NEXT: s_mov_b32 s11, s13
-; MOVREL-NEXT: s_mov_b32 s12, s14
-; MOVREL-NEXT: s_mov_b32 s13, s15
-; MOVREL-NEXT: v_mov_b32_e32 v18, s15
-; MOVREL-NEXT: v_mov_b32_e32 v17, s14
-; MOVREL-NEXT: v_mov_b32_e32 v16, s13
-; MOVREL-NEXT: v_mov_b32_e32 v15, s12
-; MOVREL-NEXT: v_mov_b32_e32 v14, s11
-; MOVREL-NEXT: v_mov_b32_e32 v13, s10
-; MOVREL-NEXT: v_mov_b32_e32 v12, s9
-; MOVREL-NEXT: v_mov_b32_e32 v11, s8
-; MOVREL-NEXT: v_mov_b32_e32 v10, s7
-; MOVREL-NEXT: v_mov_b32_e32 v9, s6
-; MOVREL-NEXT: v_mov_b32_e32 v8, s5
-; MOVREL-NEXT: v_mov_b32_e32 v7, s4
-; MOVREL-NEXT: v_mov_b32_e32 v6, s3
-; MOVREL-NEXT: v_mov_b32_e32 v5, s2
-; MOVREL-NEXT: v_mov_b32_e32 v4, s1
-; MOVREL-NEXT: v_mov_b32_e32 v3, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v5
-; MOVREL-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v12, v1, vcc_lo
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v6
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v13
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v1
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f64_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: s_mov_b32 s10, s12
+; GFX10-NEXT: s_mov_b32 s11, s13
+; GFX10-NEXT: s_mov_b32 s12, s14
+; GFX10-NEXT: s_mov_b32 s13, s15
+; GFX10-NEXT: v_mov_b32_e32 v18, s15
+; GFX10-NEXT: v_mov_b32_e32 v17, s14
+; GFX10-NEXT: v_mov_b32_e32 v16, s13
+; GFX10-NEXT: v_mov_b32_e32 v15, s12
+; GFX10-NEXT: v_mov_b32_e32 v14, s11
+; GFX10-NEXT: v_mov_b32_e32 v13, s10
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
+; GFX10-NEXT: v_mov_b32_e32 v6, s3
+; GFX10-NEXT: v_mov_b32_e32 v5, s2
+; GFX10-NEXT: v_mov_b32_e32 v4, s1
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v1, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
+; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v11, v11, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v12, v1, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s3, v6
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v4
+; GFX10-NEXT: v_readfirstlane_b32 s4, v7
+; GFX10-NEXT: v_readfirstlane_b32 s5, v8
+; GFX10-NEXT: v_readfirstlane_b32 s6, v9
+; GFX10-NEXT: v_readfirstlane_b32 s7, v10
+; GFX10-NEXT: v_readfirstlane_b32 s8, v11
+; GFX10-NEXT: v_readfirstlane_b32 s9, v2
+; GFX10-NEXT: v_readfirstlane_b32 s10, v12
+; GFX10-NEXT: v_readfirstlane_b32 s11, v13
+; GFX10-NEXT: v_readfirstlane_b32 s12, v0
+; GFX10-NEXT: v_readfirstlane_b32 s13, v1
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: s_mov_b32 s10, s12
+; GFX11-NEXT: s_mov_b32 s11, s13
+; GFX11-NEXT: s_mov_b32 s12, s14
+; GFX11-NEXT: s_mov_b32 s13, s15
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 6, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v8, v8, v1
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, v1, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v11, v11, v0 :: v_dual_cndmask_b32 v2, v12, v1
+; GFX11-NEXT: v_readfirstlane_b32 s3, v6
+; GFX11-NEXT: v_cndmask_b32_e64 v12, v13, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v13, v14, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v15, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v16, v1, s1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: v_readfirstlane_b32 s4, v7
+; GFX11-NEXT: v_readfirstlane_b32 s5, v8
+; GFX11-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-NEXT: v_readfirstlane_b32 s7, v10
+; GFX11-NEXT: v_readfirstlane_b32 s8, v11
+; GFX11-NEXT: v_readfirstlane_b32 s9, v2
+; GFX11-NEXT: v_readfirstlane_b32 s10, v12
+; GFX11-NEXT: v_readfirstlane_b32 s11, v13
+; GFX11-NEXT: v_readfirstlane_b32 s12, v0
+; GFX11-NEXT: v_readfirstlane_b32 s13, v1
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -3964,27 +5073,27 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_mov_b32_e32 v16, v15
-; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
-; MOVREL-NEXT: v_movreld_b32_e32 v0, v14
-; MOVREL-NEXT: v_movreld_b32_e32 v1, v16
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v13
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v7f64_v_v_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: v_mov_b32_e32 v16, v15
+; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v14
+; GFX10PLUS-NEXT: v_movreld_b32_e32 v1, v16
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -4030,44 +5139,76 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_v(<7 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s13, v13
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v7f64_v_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 2, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s2, 3, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s3, 4, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s4, 5, v16
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s5, 6, v16
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, v14, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v14, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v14, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v14, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v14, s5
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v15, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v7, v7, v15, s2
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v15, s3
-; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v15, s4
-; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v15, s5
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s10, v10
-; MOVREL-NEXT: v_readfirstlane_b32 s11, v11
-; MOVREL-NEXT: v_readfirstlane_b32 s12, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s13, v13
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v7f64_v_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 2, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 3, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s3, 4, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s4, 5, v16
+; GFX10-NEXT: v_cmp_eq_u32_e64 s5, 6, v16
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v14, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, v14, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v14, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v14, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v14, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v10, v10, v14, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v12, v12, v14, s5
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, v15, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v15, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, v15, s2
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v15, s3
+; GFX10-NEXT: v_cndmask_b32_e64 v11, v11, v15, s4
+; GFX10-NEXT: v_cndmask_b32_e64 v13, v13, v15, s5
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: v_readfirstlane_b32 s10, v10
+; GFX10-NEXT: v_readfirstlane_b32 s11, v11
+; GFX10-NEXT: v_readfirstlane_b32 s12, v12
+; GFX10-NEXT: v_readfirstlane_b32 s13, v13
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v7f64_v_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v14 :: v_dual_cndmask_b32 v1, v1, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v14 :: v_dual_cndmask_b32 v3, v3, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16
+; GFX11-NEXT: v_readfirstlane_b32 s2, v2
+; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v14 :: v_dual_cndmask_b32 v5, v5, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v16
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v14 :: v_dual_cndmask_b32 v7, v7, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16
+; GFX11-NEXT: v_readfirstlane_b32 s6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: v_dual_cndmask_b32 v8, v8, v14 :: v_dual_cndmask_b32 v9, v9, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v16
+; GFX11-NEXT: v_readfirstlane_b32 s8, v8
+; GFX11-NEXT: v_readfirstlane_b32 s9, v9
+; GFX11-NEXT: v_dual_cndmask_b32 v10, v10, v14 :: v_dual_cndmask_b32 v11, v11, v15
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
+; GFX11-NEXT: v_readfirstlane_b32 s10, v10
+; GFX11-NEXT: v_readfirstlane_b32 s11, v11
+; GFX11-NEXT: v_dual_cndmask_b32 v12, v12, v14 :: v_dual_cndmask_b32 v13, v13, v15
+; GFX11-NEXT: v_readfirstlane_b32 s12, v12
+; GFX11-NEXT: v_readfirstlane_b32 s13, v13
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <7 x double> %vec, double %val, i32 %idx
ret <7 x double> %insert
@@ -4088,19 +5229,19 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg
; GPRIDX-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5f64_s_s_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_cmp_eq_u32 s14, 0
-; MOVREL-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3]
-; MOVREL-NEXT: s_cmp_eq_u32 s14, 1
-; MOVREL-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5]
-; MOVREL-NEXT: s_cmp_eq_u32 s14, 2
-; MOVREL-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7]
-; MOVREL-NEXT: s_cmp_eq_u32 s14, 3
-; MOVREL-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9]
-; MOVREL-NEXT: s_cmp_eq_u32 s14, 4
-; MOVREL-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: dyn_insertelement_v5f64_s_s_s:
+; GFX10PLUS: ; %bb.0: ; %entry
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 0
+; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 1
+; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 2
+; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 3
+; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9]
+; GFX10PLUS-NEXT: s_cmp_eq_u32 s14, 4
+; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11]
+; GFX10PLUS-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -4162,60 +5303,105 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v1
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: v_mov_b32_e32 v17, s15
-; MOVREL-NEXT: v_mov_b32_e32 v16, s14
-; MOVREL-NEXT: v_mov_b32_e32 v15, s13
-; MOVREL-NEXT: v_mov_b32_e32 v14, s12
-; MOVREL-NEXT: v_mov_b32_e32 v13, s11
-; MOVREL-NEXT: v_mov_b32_e32 v12, s10
-; MOVREL-NEXT: v_mov_b32_e32 v11, s9
-; MOVREL-NEXT: v_mov_b32_e32 v10, s8
-; MOVREL-NEXT: v_mov_b32_e32 v9, s7
-; MOVREL-NEXT: v_mov_b32_e32 v8, s6
-; MOVREL-NEXT: v_mov_b32_e32 v7, s5
-; MOVREL-NEXT: v_mov_b32_e32 v6, s4
-; MOVREL-NEXT: v_mov_b32_e32 v5, s3
-; MOVREL-NEXT: v_mov_b32_e32 v4, s2
-; MOVREL-NEXT: v_mov_b32_e32 v3, s1
-; MOVREL-NEXT: v_mov_b32_e32 v2, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, s12, 1
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, s12, 4
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, s12, 3
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v4
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v5
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v1
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v5f64_s_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: v_mov_b32_e32 v17, s15
+; GFX10-NEXT: v_mov_b32_e32 v16, s14
+; GFX10-NEXT: v_mov_b32_e32 v15, s13
+; GFX10-NEXT: v_mov_b32_e32 v14, s12
+; GFX10-NEXT: v_mov_b32_e32 v13, s11
+; GFX10-NEXT: v_mov_b32_e32 v12, s10
+; GFX10-NEXT: v_mov_b32_e32 v11, s9
+; GFX10-NEXT: v_mov_b32_e32 v10, s8
+; GFX10-NEXT: v_mov_b32_e32 v9, s7
+; GFX10-NEXT: v_mov_b32_e32 v8, s6
+; GFX10-NEXT: v_mov_b32_e32 v7, s5
+; GFX10-NEXT: v_mov_b32_e32 v6, s4
+; GFX10-NEXT: v_mov_b32_e32 v5, s3
+; GFX10-NEXT: v_mov_b32_e32 v4, s2
+; GFX10-NEXT: v_mov_b32_e32 v3, s1
+; GFX10-NEXT: v_mov_b32_e32 v2, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 1
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, s12, 4
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, s12, 3
+; GFX10-NEXT: v_readfirstlane_b32 s2, v4
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v2
+; GFX10-NEXT: v_readfirstlane_b32 s1, v3
+; GFX10-NEXT: v_readfirstlane_b32 s3, v5
+; GFX10-NEXT: v_readfirstlane_b32 s4, v6
+; GFX10-NEXT: v_readfirstlane_b32 s5, v7
+; GFX10-NEXT: v_readfirstlane_b32 s6, v8
+; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s9, v1
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v5f64_s_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14
+; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12
+; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10
+; GFX11-NEXT: v_dual_mov_b32 v11, s9 :: v_dual_mov_b32 v10, s8
+; GFX11-NEXT: v_dual_mov_b32 v9, s7 :: v_dual_mov_b32 v8, s6
+; GFX11-NEXT: v_dual_mov_b32 v7, s5 :: v_dual_mov_b32 v6, s4
+; GFX11-NEXT: v_dual_mov_b32 v5, s3 :: v_dual_mov_b32 v4, s2
+; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s12, 1
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, s12, 4
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v0 :: v_dual_cndmask_b32 v3, v3, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, v0, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s12, 2
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v1, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s12, 3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v4
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v0 :: v_dual_cndmask_b32 v7, v7, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v10, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v11, v1, s1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-NEXT: v_readfirstlane_b32 s4, v6
+; GFX11-NEXT: v_readfirstlane_b32 s5, v7
+; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s8, v0
+; GFX11-NEXT: v_readfirstlane_b32 s9, v1
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -4277,60 +5463,105 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v1
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5f64_s_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: s_mov_b32 s0, s2
-; MOVREL-NEXT: s_mov_b32 s1, s3
-; MOVREL-NEXT: s_mov_b32 s2, s4
-; MOVREL-NEXT: s_mov_b32 s3, s5
-; MOVREL-NEXT: s_mov_b32 s4, s6
-; MOVREL-NEXT: s_mov_b32 s5, s7
-; MOVREL-NEXT: s_mov_b32 s6, s8
-; MOVREL-NEXT: s_mov_b32 s7, s9
-; MOVREL-NEXT: s_mov_b32 s8, s10
-; MOVREL-NEXT: s_mov_b32 s9, s11
-; MOVREL-NEXT: v_mov_b32_e32 v18, s15
-; MOVREL-NEXT: v_mov_b32_e32 v17, s14
-; MOVREL-NEXT: v_mov_b32_e32 v16, s13
-; MOVREL-NEXT: v_mov_b32_e32 v15, s12
-; MOVREL-NEXT: v_mov_b32_e32 v14, s11
-; MOVREL-NEXT: v_mov_b32_e32 v13, s10
-; MOVREL-NEXT: v_mov_b32_e32 v12, s9
-; MOVREL-NEXT: v_mov_b32_e32 v11, s8
-; MOVREL-NEXT: v_mov_b32_e32 v10, s7
-; MOVREL-NEXT: v_mov_b32_e32 v9, s6
-; MOVREL-NEXT: v_mov_b32_e32 v8, s5
-; MOVREL-NEXT: v_mov_b32_e32 v7, s4
-; MOVREL-NEXT: v_mov_b32_e32 v6, s3
-; MOVREL-NEXT: v_mov_b32_e32 v5, s2
-; MOVREL-NEXT: v_mov_b32_e32 v4, s1
-; MOVREL-NEXT: v_mov_b32_e32 v3, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s1, 4, v2
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
-; MOVREL-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
-; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v5
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0
-; MOVREL-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1
-; MOVREL-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v3
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v7
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v9
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v1
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v5f64_s_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_mov_b32 s0, s2
+; GFX10-NEXT: s_mov_b32 s1, s3
+; GFX10-NEXT: s_mov_b32 s2, s4
+; GFX10-NEXT: s_mov_b32 s3, s5
+; GFX10-NEXT: s_mov_b32 s4, s6
+; GFX10-NEXT: s_mov_b32 s5, s7
+; GFX10-NEXT: s_mov_b32 s6, s8
+; GFX10-NEXT: s_mov_b32 s7, s9
+; GFX10-NEXT: s_mov_b32 s8, s10
+; GFX10-NEXT: s_mov_b32 s9, s11
+; GFX10-NEXT: v_mov_b32_e32 v18, s15
+; GFX10-NEXT: v_mov_b32_e32 v17, s14
+; GFX10-NEXT: v_mov_b32_e32 v16, s13
+; GFX10-NEXT: v_mov_b32_e32 v15, s12
+; GFX10-NEXT: v_mov_b32_e32 v14, s11
+; GFX10-NEXT: v_mov_b32_e32 v13, s10
+; GFX10-NEXT: v_mov_b32_e32 v12, s9
+; GFX10-NEXT: v_mov_b32_e32 v11, s8
+; GFX10-NEXT: v_mov_b32_e32 v10, s7
+; GFX10-NEXT: v_mov_b32_e32 v9, s6
+; GFX10-NEXT: v_mov_b32_e32 v8, s5
+; GFX10-NEXT: v_mov_b32_e32 v7, s4
+; GFX10-NEXT: v_mov_b32_e32 v6, s3
+; GFX10-NEXT: v_mov_b32_e32 v5, s2
+; GFX10-NEXT: v_mov_b32_e32 v4, s1
+; GFX10-NEXT: v_mov_b32_e32 v3, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX10-NEXT: v_cmp_eq_u32_e64 s1, 4, v2
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
+; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX10-NEXT: v_readfirstlane_b32 s2, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v0, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v1, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1
+; GFX10-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v3
+; GFX10-NEXT: v_readfirstlane_b32 s1, v4
+; GFX10-NEXT: v_readfirstlane_b32 s3, v6
+; GFX10-NEXT: v_readfirstlane_b32 s4, v7
+; GFX10-NEXT: v_readfirstlane_b32 s5, v2
+; GFX10-NEXT: v_readfirstlane_b32 s6, v8
+; GFX10-NEXT: v_readfirstlane_b32 s7, v9
+; GFX10-NEXT: v_readfirstlane_b32 s8, v0
+; GFX10-NEXT: v_readfirstlane_b32 s9, v1
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v5f64_s_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_mov_b32 s0, s2
+; GFX11-NEXT: s_mov_b32 s1, s3
+; GFX11-NEXT: s_mov_b32 s2, s4
+; GFX11-NEXT: s_mov_b32 s3, s5
+; GFX11-NEXT: s_mov_b32 s4, s6
+; GFX11-NEXT: s_mov_b32 s5, s7
+; GFX11-NEXT: s_mov_b32 s6, s8
+; GFX11-NEXT: s_mov_b32 s7, s9
+; GFX11-NEXT: s_mov_b32 s8, s10
+; GFX11-NEXT: s_mov_b32 s9, s11
+; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14
+; GFX11-NEXT: v_dual_mov_b32 v16, s13 :: v_dual_mov_b32 v15, s12
+; GFX11-NEXT: v_dual_mov_b32 v14, s11 :: v_dual_mov_b32 v13, s10
+; GFX11-NEXT: v_dual_mov_b32 v12, s9 :: v_dual_mov_b32 v11, s8
+; GFX11-NEXT: v_dual_mov_b32 v10, s7 :: v_dual_mov_b32 v9, s6
+; GFX11-NEXT: v_dual_mov_b32 v8, s5 :: v_dual_mov_b32 v7, s4
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v5, s2
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v2
+; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 4, v2
+; GFX11-NEXT: v_dual_cndmask_b32 v3, v3, v0 :: v_dual_cndmask_b32 v4, v4, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v0, s0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v2
+; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, v1, s0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v2
+; GFX11-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v7, v7, v0 :: v_dual_cndmask_b32 v2, v8, v1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v9, v0, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v10, v1, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v11, v0, s1
+; GFX11-NEXT: v_cndmask_b32_e64 v1, v12, v1, s1
+; GFX11-NEXT: v_readfirstlane_b32 s0, v3
+; GFX11-NEXT: v_readfirstlane_b32 s1, v4
+; GFX11-NEXT: v_readfirstlane_b32 s3, v6
+; GFX11-NEXT: v_readfirstlane_b32 s4, v7
+; GFX11-NEXT: v_readfirstlane_b32 s5, v2
+; GFX11-NEXT: v_readfirstlane_b32 s6, v8
+; GFX11-NEXT: v_readfirstlane_b32 s7, v9
+; GFX11-NEXT: v_readfirstlane_b32 s8, v0
+; GFX11-NEXT: v_readfirstlane_b32 s9, v1
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -4366,34 +5597,59 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_s:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 4
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 0
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, s2, 4
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 1
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 2
+; GFX11-NEXT: v_readfirstlane_b32 s8, v8
+; GFX11-NEXT: v_readfirstlane_b32 s9, v9
+; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
+; GFX11-NEXT: v_cmp_eq_u32_e64 vcc_lo, s2, 3
+; GFX11-NEXT: v_readfirstlane_b32 s2, v2
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
+; GFX11-NEXT: v_readfirstlane_b32 s6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
@@ -4429,34 +5685,59 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_v(<5 x double> %vec,
; GPRIDX-NEXT: v_readfirstlane_b32 s9, v9
; GPRIDX-NEXT: ; return to shader part epilog
;
-; MOVREL-LABEL: dyn_insertelement_v5f64_v_v_v:
-; MOVREL: ; %bb.0: ; %entry
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
-; MOVREL-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s0, v0
-; MOVREL-NEXT: v_readfirstlane_b32 s1, v1
-; MOVREL-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s2, v2
-; MOVREL-NEXT: v_readfirstlane_b32 s3, v3
-; MOVREL-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s4, v4
-; MOVREL-NEXT: v_readfirstlane_b32 s5, v5
-; MOVREL-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
-; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
-; MOVREL-NEXT: v_readfirstlane_b32 s6, v6
-; MOVREL-NEXT: v_readfirstlane_b32 s7, v7
-; MOVREL-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
-; MOVREL-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
-; MOVREL-NEXT: v_readfirstlane_b32 s8, v8
-; MOVREL-NEXT: v_readfirstlane_b32 s9, v9
-; MOVREL-NEXT: ; return to shader part epilog
+; GFX10-LABEL: dyn_insertelement_v5f64_v_v_v:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
+; GFX10-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v1, v1, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX10-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
+; GFX10-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10-NEXT: v_cndmask_b32_e32 v4, v4, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
+; GFX10-NEXT: v_readfirstlane_b32 s4, v4
+; GFX10-NEXT: v_readfirstlane_b32 s5, v5
+; GFX10-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc_lo
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v12
+; GFX10-NEXT: v_readfirstlane_b32 s6, v6
+; GFX10-NEXT: v_readfirstlane_b32 s7, v7
+; GFX10-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc_lo
+; GFX10-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX10-NEXT: v_readfirstlane_b32 s8, v8
+; GFX10-NEXT: v_readfirstlane_b32 s9, v9
+; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: dyn_insertelement_v5f64_v_v_v:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v12
+; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 4, v12
+; GFX11-NEXT: v_dual_cndmask_b32 v0, v0, v10 :: v_dual_cndmask_b32 v1, v1, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v12
+; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, v10, s0
+; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v11, s0
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: v_readfirstlane_b32 s1, v1
+; GFX11-NEXT: v_dual_cndmask_b32 v2, v2, v10 :: v_dual_cndmask_b32 v3, v3, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v12
+; GFX11-NEXT: v_readfirstlane_b32 s8, v8
+; GFX11-NEXT: v_readfirstlane_b32 s9, v9
+; GFX11-NEXT: v_readfirstlane_b32 s2, v2
+; GFX11-NEXT: v_readfirstlane_b32 s3, v3
+; GFX11-NEXT: v_dual_cndmask_b32 v4, v4, v10 :: v_dual_cndmask_b32 v5, v5, v11
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v12
+; GFX11-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-NEXT: v_readfirstlane_b32 s5, v5
+; GFX11-NEXT: v_dual_cndmask_b32 v6, v6, v10 :: v_dual_cndmask_b32 v7, v7, v11
+; GFX11-NEXT: v_readfirstlane_b32 s6, v6
+; GFX11-NEXT: v_readfirstlane_b32 s7, v7
+; GFX11-NEXT: ; return to shader part epilog
entry:
%insert = insertelement <5 x double> %vec, double %val, i32 %idx
ret <5 x double> %insert
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
index 1fa75feb9d83..419bdb2076cc 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
@@ -1,80 +1,138 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
-; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX10
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX10
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GFX11
define i32 @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: global_atomic_csub:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: global_atomic_csub:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
ret i32 %ret
}
define i32 @global_atomic_csub_offset(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub_offset:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_mov_b64 s[4:5], 0x1000
-; GCN-NEXT: v_mov_b32_e32 v3, s4
-; GCN-NEXT: v_mov_b32_e32 v4, s5
-; GCN-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
-; GCN-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
-; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: global_atomic_csub_offset:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_mov_b64 s[4:5], 0x1000
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s5
+; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
+; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: global_atomic_csub_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_mov_b64 s[0:1], 0x1000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
+; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
ret i32 %ret
}
define void @global_atomic_csub_nortn(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub_nortn:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: global_atomic_csub_nortn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: global_atomic_csub_nortn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %ptr, i32 %data)
ret void
}
define void @global_atomic_csub_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub_offset_nortn:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: s_mov_b64 s[4:5], 0x1000
-; GCN-NEXT: v_mov_b32_e32 v3, s4
-; GCN-NEXT: v_mov_b32_e32 v4, s5
-; GCN-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
-; GCN-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
-; GCN-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: global_atomic_csub_offset_nortn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_mov_b64 s[4:5], 0x1000
+; GFX10-NEXT: v_mov_b32_e32 v3, s4
+; GFX10-NEXT: v_mov_b32_e32 v4, s5
+; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
+; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
+; GFX10-NEXT: global_atomic_csub v0, v[0:1], v2, off glc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: global_atomic_csub_offset_nortn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_mov_b64 s[0:1], 0x1000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0
+; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
+; GFX11-NEXT: global_atomic_csub_u32 v0, v[0:1], v2, off glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
ret void
}
define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub_sgpr_base_offset:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: s_load_dword s2, s[4:5], 0x8
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GCN-NEXT: v_mov_b32_e32 v1, 0x1000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
-; GCN-NEXT: s_waitcnt vmcnt(0)
-; GCN-NEXT: global_store_dword v[0:1], v0, off
-; GCN-NEXT: s_endpgm
+; GFX10-LABEL: global_atomic_csub_sgpr_base_offset:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x1000
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
+; GFX10-NEXT: s_waitcnt vmcnt(0)
+; GFX10-NEXT: global_store_dword v[0:1], v0, off
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: global_atomic_csub_sgpr_base_offset:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0x1000 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: global_atomic_csub_u32 v0, v1, v0, s[0:1] glc
+; GFX11-NEXT: s_waitcnt vmcnt(0)
+; GFX11-NEXT: global_store_b32 v[0:1], v0, off
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
store i32 %ret, i32 addrspace(1)* undef
@@ -82,16 +140,27 @@ define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset(i32 addrspace(1)*
}
define amdgpu_kernel void @global_atomic_csub_sgpr_base_offset_nortn(i32 addrspace(1)* %ptr, i32 %data) {
-; GCN-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_clause 0x1
-; GCN-NEXT: s_load_dword s2, s[4:5], 0x8
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
-; GCN-NEXT: v_mov_b32_e32 v1, 0x1000
-; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
-; GCN-NEXT: s_endpgm
+; GFX10-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dword s2, s[4:5], 0x8
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0x1000
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_mov_b32_e32 v0, s2
+; GFX10-NEXT: global_atomic_csub v0, v1, v0, s[0:1] glc
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: global_atomic_csub_sgpr_base_offset_nortn:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_dual_mov_b32 v1, 0x1000 :: v_dual_mov_b32 v0, s2
+; GFX11-NEXT: global_atomic_csub_u32 v0, v1, v0, s[0:1] glc
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
%gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
%ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
index 57983e07ccad..608746f71e18 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
@@ -2,7 +2,8 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define double @v_trig_preop_f64(double %a, i32 %b) {
; GCN-LABEL: v_trig_preop_f64:
@@ -11,12 +12,12 @@ define double @v_trig_preop_f64(double %a, i32 %b) {
; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_trig_preop_f64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_trig_preop_f64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
ret double %result
}
@@ -28,12 +29,12 @@ define double @v_trig_preop_f64_imm(double %a, i32 %b) {
; GCN-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7
; GCN-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_trig_preop_f64_imm:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_trig_preop_f64_imm:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_trig_preop_f64 v[0:1], v[0:1], 7
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
ret double %result
}
@@ -82,6 +83,18 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) {
; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_trig_preop_f64:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
+; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x8
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[2:3], s0
+; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
store volatile double %result, double* undef
ret void
@@ -105,6 +118,16 @@ define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
; GFX10-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_trig_preop_f64_imm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
+; GFX11-NEXT: flat_store_b64 v[0:1], v[0:1] dlc
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
store volatile double %result, double* undef
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
index f397be139a8d..4d22c4a239aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10PLUS,GFX11 %s
define i32 @v_udot4(i32 %a, i32 %b, i32 %c) {
; GFX906-LABEL: v_udot4:
@@ -10,12 +11,12 @@ define i32 @v_udot4(i32 %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot4:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot4:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 false)
ret i32 %r
}
@@ -27,12 +28,12 @@ define i32 @v_udot4_clamp(i32 %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot4_clamp:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot4_clamp:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%r = call i32 @llvm.amdgcn.udot4(i32 %a, i32 %b, i32 %c, i1 true)
ret i32 %r
}
@@ -82,6 +83,29 @@ define i32 @v_udot4_cast_v4i8(<4 x i8> %a, <4 x i8> %b, i32 %c) {
; GFX10-NEXT: v_or3_b32 v1, v3, v4, v5
; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v8
; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_udot4_cast_v4i8:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
+; GFX11-NEXT: v_and_b32_e32 v5, 0xff, v5
+; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 8, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 8, v5
+; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-NEXT: v_lshlrev_b32_e32 v3, 24, v3
+; GFX11-NEXT: v_and_or_b32 v0, v0, 0xff, v1
+; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v6
+; GFX11-NEXT: v_and_b32_e32 v6, 0xff, v7
+; GFX11-NEXT: v_and_or_b32 v4, v4, 0xff, v5
+; GFX11-NEXT: v_or3_b32 v0, v0, v2, v3
+; GFX11-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-NEXT: v_lshlrev_b32_e32 v5, 24, v6
+; GFX11-NEXT: v_or3_b32 v1, v4, v1, v5
+; GFX11-NEXT: v_dot4_u32_u8 v0, v0, v1, v8
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%a.cast = bitcast <4 x i8> %a to i32
%b.cast = bitcast <4 x i8> %b to i32
%r = call i32 @llvm.amdgcn.udot4(i32 %a.cast, i32 %b.cast, i32 %c, i1 false)
@@ -96,13 +120,13 @@ define i32 @v_udot4_fnegf32_a(float %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot4_fnegf32_a:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot4_fnegf32_a:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%cast.neg.a = bitcast float %neg.a to i32
%r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
@@ -117,13 +141,13 @@ define i32 @v_udot4_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot4_fnegv2f16_a:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot4_fnegv2f16_a:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX10PLUS-NEXT: v_dot4_u32_u8 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg <2 x half> %a
%cast.neg.a = bitcast <2 x half> %neg.a to i32
%r = call i32 @llvm.amdgcn.udot4(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
index 14eec52f4c93..6317f67fd8d1 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
@@ -1,7 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX906 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1011 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1012 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10PLUS %s
define i32 @v_udot8(i32 %a, i32 %b, i32 %c) {
; GFX906-LABEL: v_udot8:
@@ -10,12 +11,12 @@ define i32 @v_udot8(i32 %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot8:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot8:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 false)
ret i32 %r
}
@@ -27,12 +28,12 @@ define i32 @v_udot8_clamp(i32 %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot8_clamp:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot8_clamp:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2 clamp
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%r = call i32 @llvm.amdgcn.udot8(i32 %a, i32 %b, i32 %c, i1 true)
ret i32 %r
}
@@ -53,13 +54,13 @@ define i32 @v_udot8_fnegf32_a(float %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot8_fnegf32_a:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
-; GFX10-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot8_fnegf32_a:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
+; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg float %a
%cast.neg.a = bitcast float %neg.a to i32
%r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
@@ -74,13 +75,13 @@ define i32 @v_udot8_fnegv2f16_a(<2 x half> %a, i32 %b, i32 %c) {
; GFX906-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
; GFX906-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_udot8_fnegv2f16_a:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
-; GFX10-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_udot8_fnegv2f16_a:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10PLUS-NEXT: v_xor_b32_e32 v0, 0x80008000, v0
+; GFX10PLUS-NEXT: v_dot8_u32_u4 v0, v0, v1, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%neg.a = fneg <2 x half> %a
%cast.neg.a = bitcast <2 x half> %neg.a to i32
%r = call i32 @llvm.amdgcn.udot8(i32 %cast.neg.a, i32 %b, i32 %c, i1 false)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
index e89fa4424bab..3dca12d771f1 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll
@@ -1,14 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s
-; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
+; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11 %s
define float @v_fma(float %a, float %b, float %c) {
-; GCN-LABEL: v_fma:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: v_fma_legacy_f32 v0, v0, v1, v2
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fma_legacy_f32 v0, v0, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fma:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fma_dx9_zero_f32 v0, v0, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %c)
ret float %fma
}
@@ -21,29 +30,59 @@ define float @v_fma_imm(float %a, float %c) {
; GCN-NEXT: v_fmac_legacy_f32_e32 v1, 0x41200000, v0
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma_imm:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fmac_legacy_f32_e32 v1, 0x41200000, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, v1
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fma_imm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fmac_dx9_zero_f32_e32 v1, 0x41200000, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_mov_b32_e32 v0, v1
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float 10.0, float %c)
ret float %fma
}
define float @v_fabs_fma(float %a, float %b, float %c) {
-; GCN-LABEL: v_fabs_fma:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: v_fma_legacy_f32 v0, |v0|, v1, v2
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fabs_fma:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fma_legacy_f32 v0, |v0|, v1, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fabs_fma:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fma_dx9_zero_f32 v0, |v0|, v1, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.a = call float @llvm.fabs.f32(float %a)
%fma = call float @llvm.amdgcn.fma.legacy(float %fabs.a, float %b, float %c)
ret float %fma
}
define float @v_fneg_fabs_fma(float %a, float %b, float %c) {
-; GCN-LABEL: v_fneg_fabs_fma:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: v_fma_legacy_f32 v0, v0, -|v1|, v2
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fneg_fabs_fma:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fma_legacy_f32 v0, v0, -|v1|, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fabs_fma:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fma_dx9_zero_f32 v0, v0, -|v1|, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fabs.b = call float @llvm.fabs.f32(float %b)
%neg.fabs.b = fneg float %fabs.b
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float %neg.fabs.b, float %c)
@@ -51,24 +90,38 @@ define float @v_fneg_fabs_fma(float %a, float %b, float %c) {
}
define float @v_fneg_fma(float %a, float %b, float %c) {
-; GCN-LABEL: v_fneg_fma:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: v_fma_legacy_f32 v0, v0, v1, -v2
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fneg_fma:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fma_legacy_f32 v0, v0, v1, -v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fneg_fma:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fma_dx9_zero_f32 v0, v0, v1, -v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%neg.c = fneg float %c
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %neg.c)
ret float %fma
}
define float @v_fma_const_const(float %a) {
-; GCN-LABEL: v_fma_const_const:
-; GCN: ; %bb.0:
-; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT: s_waitcnt_vscnt null, 0x0
-; GCN-NEXT: v_fma_legacy_f32 v0, v0, 2.0, -1.0
-; GCN-NEXT: s_setpc_b64 s[30:31]
+; GFX10-LABEL: v_fma_const_const:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: v_fma_legacy_f32 v0, v0, 2.0, -1.0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fma_const_const:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX11-NEXT: v_fma_dx9_zero_f32 v0, v0, 2.0, -1.0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
%fma = call float @llvm.amdgcn.fma.legacy(float %a, float 2.0, float -1.0)
ret float %fma
}
diff --git a/llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir b/llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
index aef3eed2b52b..b7e1dfb2eda2 100644
--- a/llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
+++ b/llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -o - -run-pass=block-placement -mcpu=gfx1010 -mattr=-inst-fwd-prefetch-bug -verify-machineinstrs %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -o - -run-pass=block-placement -mcpu=gfx1010 -mattr=-inst-fwd-prefetch-bug -verify-machineinstrs %s | FileCheck -check-prefixes=GFX10 %s
+# RUN: llc -march=amdgcn -o - -run-pass=block-placement -mcpu=gfx1100 -mattr=-inst-fwd-prefetch-bug -verify-machineinstrs %s | FileCheck -check-prefixes=GFX11 %s
# Used to fail with
# Assertion `Out && "Header of loop has no predecessors from outside loop?"
@@ -7,41 +8,76 @@
---
name: loop_header_nopred
body: |
- ; GCN-LABEL: name: loop_header_nopred
- ; GCN: bb.0:
- ; GCN-NEXT: successors: %bb.2(0x80000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_BRANCH %bb.2
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.1 (align 64):
- ; GCN-NEXT: successors: %bb.7(0x04000000), %bb.2(0x7c000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit $vcc_lo
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.2:
- ; GCN-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.5:
- ; GCN-NEXT: successors: %bb.1(0x04000000), %bb.5(0x7c000000)
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_NOP 0
- ; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
- ; GCN-NEXT: S_BRANCH %bb.1
- ; GCN-NEXT: {{ $}}
- ; GCN-NEXT: bb.7:
- ; GCN-NEXT: S_ENDPGM 0
+ ; GFX10-LABEL: name: loop_header_nopred
+ ; GFX10: bb.0:
+ ; GFX10-NEXT: successors: %bb.2(0x80000000)
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: S_BRANCH %bb.2
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: bb.1 (align 64):
+ ; GFX10-NEXT: successors: %bb.7(0x04000000), %bb.2(0x7c000000)
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit $vcc_lo
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: bb.2:
+ ; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000)
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: bb.5:
+ ; GFX10-NEXT: successors: %bb.1(0x04000000), %bb.5(0x7c000000)
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_NOP 0
+ ; GFX10-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
+ ; GFX10-NEXT: S_BRANCH %bb.1
+ ; GFX10-NEXT: {{ $}}
+ ; GFX10-NEXT: bb.7:
+ ; GFX10-NEXT: S_ENDPGM 0
+ ; GFX11-LABEL: name: loop_header_nopred
+ ; GFX11: bb.0:
+ ; GFX11-NEXT: successors: %bb.2(0x80000000)
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: S_BRANCH %bb.2
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: bb.1:
+ ; GFX11-NEXT: successors: %bb.7(0x04000000), %bb.2(0x7c000000)
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit $vcc_lo
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: bb.2:
+ ; GFX11-NEXT: successors: %bb.5(0x40000000), %bb.1(0x40000000)
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: bb.5:
+ ; GFX11-NEXT: successors: %bb.1(0x04000000), %bb.5(0x7c000000)
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_NOP 0
+ ; GFX11-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
+ ; GFX11-NEXT: S_BRANCH %bb.1
+ ; GFX11-NEXT: {{ $}}
+ ; GFX11-NEXT: bb.7:
+ ; GFX11-NEXT: S_ENDPGM 0
bb.0:
successors: %bb.1(0x80000000)
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