[PATCH] D128835: [AArch64] Add support for various operations on nxv1i1 types.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen updated this revision to Diff 442456.
sdesmalen marked an inline comment as done.
sdesmalen added a comment.

Use Pg instead of creating a new predicate for VECREDUCE_XOR.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128835/new/

https://reviews.llvm.org/D128835

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-int-log.ll
  llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-reinterpret.ll

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