[PATCH] D128835: [AArch64] Add support for various operations on nxv1i1 types.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20979
+      Pg = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1,
+                       DAG.getConstant(1, DL, MVT::nxv1i1));
+      Op = DAG.getNode(AArch64ISD::REINTERPRET_CAST, DL, MVT::nxv2i1, Op);
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Can this be `Pg` because you've updated `getPTrue` so `getPredicateForVector` should do the right thing?


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Comment at: llvm/test/CodeGen/AArch64/sve-int-pred-reduce.ll:112-114
+; CHECK-NEXT:    ptest p0, p0.b
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
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Given this patch fixes the xor reductions is it worth merging this patch with D129081?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128835/new/

https://reviews.llvm.org/D128835