[PATCH] D129095: [AMDGPU][CodeGen] Match complex register SMRD offsets.

[Ivan Kosarev via Phabricator via llvm-commits]

kosarev created this revision.
kosarev added reviewers: dp, foad, arsenm, rampitec.
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Saves some add instructions on a couple Rage 2 shaders and is also a
prerequisite for a coming-soon change matching (register + immediate)
offsets.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129095

Files:
  llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll


Index: llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
+++ llvm/test/CodeGen/AMDGPU/amdgcn-load-offset-from-reg.ll
@@ -1,11 +1,13 @@
-; Test that DAG->DAG ISel is able to pick up the S_LOAD_DWORDX4_SGPR instruction that fetches the offset
-; from a register.
-
 ; RUN: llc -march=amdgcn -verify-machineinstrs -stop-after=amdgpu-isel -o - %s | FileCheck -check-prefix=GCN %s
 
+ at 0 = external dso_local addrspace(4) constant [4 x <2 x float>]
+ at 1 = external dso_local addrspace(4) constant i32
+
+; Test that DAG->DAG ISel is able to pick up the S_LOAD_DWORDX4_SGPR instruction that fetches the offset
+; from a register.
+; GCN-LABEL: name: test_load_zext
 ; GCN: %[[OFFSET:[0-9]+]]:sreg_32 = S_MOV_B32 target-flags(amdgpu-abs32-lo) @DescriptorBuffer
 ; GCN: %{{[0-9]+}}:sgpr_128 = S_LOAD_DWORDX4_SGPR killed %{{[0-9]+}}, killed %[[OFFSET]], 0 :: (invariant load (s128) from %ir.13, addrspace 4)
-
 define amdgpu_cs void @test_load_zext(i32 inreg %0, i32 inreg %1, i32 inreg %resNode0, i32 inreg %resNode1, <3 x i32> inreg %2, i32 inreg %3, <3 x i32> %4) local_unnamed_addr #2 {
 .entry:
   %5 = call i64 @llvm.amdgcn.s.getpc() #3
@@ -23,6 +25,21 @@
   ret void
 }
 
+; Make sure we match complex register offsets, which may come before the
+; base operand in the load's SDAG nodes.
+; GCN-LABEL: name: test_complex_reg_offset
+; GCN: S_LOAD_DWORD_IMM
+; GCN: S_LOAD_DWORD_SGPR
+define amdgpu_ps void @test_complex_reg_offset(float addrspace(1)* %out) {
+  %i = load i32, i32 addrspace(4)* @1
+  %1 = and i32 %i, 3
+  %2 = zext i32 %1 to i64
+  %3 = getelementptr [4 x <2 x float>], [4 x <2 x float>] addrspace(4)* @0, i64 0, i64 %2, i64 0
+  %4 = load float, float addrspace(4)* %3, align 4
+  store float %4, float addrspace(1)* %out
+  ret void
+}
+
 declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #1
 
 ; Function Attrs: nounwind readnone speculatable
Index: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -1981,6 +1981,10 @@
         SBase = Expand32BitAddress(N0);
         return true;
       }
+      if (SelectSMRDOffset(N0, Offset, Imm)) {
+        SBase = Expand32BitAddress(N1);
+        return true;
+      }
     }
   }
   SBase = Expand32BitAddress(Addr);


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