[PATCH] D128642: [AArch64][SVE] Use SVE for VLS fcopysign for wide vectors

[Peter Waller via Phabricator via llvm-commits]

peterwaller-arm accepted this revision.
peterwaller-arm added a comment.
This revision is now accepted and ready to land.

Looking generally good but I see some possible minor improvements/cleanup.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7591
 
+  if (isFixedSVE) {
+    assert(isTypeLegal(VT) && "Expected only legal fixed-width types");
----------------
Nit: Does `isFixedSVE` want to move down with the use?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:7661
+    VT = Op.getValueType();
+    IntVT = VT.changeTypeToInteger();
+    BSP = convertFromScalableVector(DAG, IntVT, BSP);
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Is this line necessary or could it be pushed up? At a glance it appears it should already be an integer VT derived from VT. Same question for the VT assignment.


Repository:
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  https://reviews.llvm.org/D128642/new/

https://reviews.llvm.org/D128642