[PATCH] D129072: [RISCV] Fix the scale of getIntMatCost and also need adjust for getIntImmCost

[Zixuan Wu via Phabricator via llvm-commits]

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As getInstSeqCost calculates the cost of instruction sequence with considering the RVC instruction, it multiplies a factor 100 to distinguish the compressed instruction cost. And getIntMatCost should adopt the same scale.

But the TargetTransformInfo just models the cost with the num of instruction as usual. So it needs to adjust the cost by / 100 to match.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129072

Files:
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
  llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
  llvm/test/CodeGen/RISCV/add-before-shl.ll


Index: llvm/test/CodeGen/RISCV/add-before-shl.ll
===================================================================
--- llvm/test/CodeGen/RISCV/add-before-shl.ll
+++ llvm/test/CodeGen/RISCV/add-before-shl.ll
@@ -196,25 +196,25 @@
 ;
 ; RV32C-LABEL: add_wide_operand:
 ; RV32C:       # %bb.0:
-; RV32C-NEXT:    c.lw a2, 4(a1)
-; RV32C-NEXT:    c.lw a3, 12(a1)
-; RV32C-NEXT:    c.lw a4, 0(a1)
-; RV32C-NEXT:    c.lw a1, 8(a1)
-; RV32C-NEXT:    c.lui a5, 16
-; RV32C-NEXT:    c.add a3, a5
-; RV32C-NEXT:    c.slli a3, 3
+; RV32C-NEXT:    c.lw a2, 12(a1)
+; RV32C-NEXT:    c.lw a3, 8(a1)
+; RV32C-NEXT:    c.lw a4, 4(a1)
+; RV32C-NEXT:    c.lw a1, 0(a1)
+; RV32C-NEXT:    c.slli a2, 3
+; RV32C-NEXT:    srli a5, a3, 29
+; RV32C-NEXT:    c.or a2, a5
+; RV32C-NEXT:    lui a5, 128
+; RV32C-NEXT:    add a6, a2, a5
 ; RV32C-NEXT:    srli a5, a1, 29
-; RV32C-NEXT:    or a6, a3, a5
-; RV32C-NEXT:    srli a5, a4, 29
-; RV32C-NEXT:    slli a3, a2, 3
-; RV32C-NEXT:    c.or a3, a5
-; RV32C-NEXT:    c.srli a2, 29
-; RV32C-NEXT:    c.slli a1, 3
-; RV32C-NEXT:    c.or a1, a2
 ; RV32C-NEXT:    slli a2, a4, 3
-; RV32C-NEXT:    c.sw a2, 0(a0)
-; RV32C-NEXT:    c.sw a1, 8(a0)
-; RV32C-NEXT:    c.sw a3, 4(a0)
+; RV32C-NEXT:    c.or a2, a5
+; RV32C-NEXT:    c.srli a4, 29
+; RV32C-NEXT:    c.slli a3, 3
+; RV32C-NEXT:    c.or a3, a4
+; RV32C-NEXT:    c.slli a1, 3
+; RV32C-NEXT:    c.sw a1, 0(a0)
+; RV32C-NEXT:    c.sw a3, 8(a0)
+; RV32C-NEXT:    c.sw a2, 4(a0)
 ; RV32C-NEXT:    sw a6, 12(a0)
 ; RV32C-NEXT:    c.jr ra
 ;
Index: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -35,7 +35,7 @@
   // Otherwise, we check how many instructions it will take to materialise.
   const DataLayout &DL = getDataLayout();
   return RISCVMatInt::getIntMatCost(Imm, DL.getTypeSizeInBits(Ty),
-                                    getST()->getFeatureBits());
+                                    getST()->getFeatureBits()) / 100;
 }
 
 InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -14,7 +14,7 @@
 
 static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
   if (!HasRVC)
-    return Res.size();
+    return Res.size() * 100;
 
   int Cost = 0;
   for (auto Instr : Res) {
@@ -392,7 +392,7 @@
     InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), ActiveFeatures);
     Cost += getInstSeqCost(MatSeq, HasRVC);
   }
-  return std::max(1, Cost);
+  return std::max(100, Cost);
 }
 
 OpndKind Inst::getOpndKind() const {


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