[PATCH] D128188: [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
luxufan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 3 06:04:06 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0f45eaf0da1f: [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset (authored by StephenFan).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128188/new/
https://reviews.llvm.org/D128188
Files:
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
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