[PATCH] D128188: [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 1 09:07:27 PDT 2022
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir:125
; RV64: # %bb.0:
- ; RV64-NEXT: addi sp, sp, -48
- ; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
- ; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
- ; RV64-NEXT: addi s0, sp, 48
+ ; RV64-NEXT: addi sp, sp, -80
+ ; RV64-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
----------------
frasercrmck wrote:
> What's causing changes in these tests?
We're allocating an emergency spill slot because there is an ADDI frame index reference to a scalable slot. We weren't considering ADDI before.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128188/new/
https://reviews.llvm.org/D128188
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