[PATCH] D118302: [Spill2Reg][5/9] Code generation part 2.

[Vasileios Porpodas via Phabricator via llvm-commits]

vporpo updated this revision to Diff 441839.
vporpo added a comment.

Added spill2reg_simple_3.mir test to check `-spill2reg-mem-instrs`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D118302/new/

https://reviews.llvm.org/D118302

Files:
  llvm/lib/CodeGen/Spill2Reg.cpp
  llvm/test/CodeGen/X86/spill2reg_avoid_vector_instrs.mir
  llvm/test/CodeGen/X86/spill2reg_disable_when_noimplicitfloat.mir
  llvm/test/CodeGen/X86/spill2reg_mask_spills.mir
  llvm/test/CodeGen/X86/spill2reg_simple_1_32bit.mir
  llvm/test/CodeGen/X86/spill2reg_simple_1_64bit.mir
  llvm/test/CodeGen/X86/spill2reg_simple_2.mir
  llvm/test/CodeGen/X86/spill2reg_simple_3.mir

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