[PATCH] D118302: [Spill2Reg][5/9] Code generation part 2.

[Guozhi Wei via Phabricator via llvm-commits]

Carrot added inline comments.


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Comment at: llvm/test/CodeGen/X86/spill2reg_simple_2.mir:2
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc %s -o - -mtriple=x86_64-unknown-linux -enable-spill2reg -mattr=+sse4.1 --run-pass=spill2reg -simplify-mir -spill2reg-mem-instrs=0 -spill2reg-vec-instrs=99999 | FileCheck %s
+
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All test cases have the option -spill2reg-mem-instrs=0. It looks to me more like a debug purpose option. A more practical and positive performance impact value should be larger than 0. Could you add a test case for it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D118302/new/

https://reviews.llvm.org/D118302