[PATCH] D128934: [X86] Add RDPRU instruction
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 30 19:54:59 PDT 2022
craig.topper added a comment.
32-bit codegen looks ok. 64-bit values are returned in edx:eax like the instruction.
================
Comment at: llvm/lib/Target/X86/X86InstrSystem.td:742
+let Uses = [ECX], Defs = [EAX, EDX] in
+ def RDPRU : I<0x01, MRM_FD, (outs), (ins), "rdpru", []>, TB,
+ Requires<[HasRDPRU]>;
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probinson wrote:
> craig.topper wrote:
> > I think `TB` here should be `PS`. Per table "Table A-8. Opcode 01h ModRM Extensions", the instruction is not valid with a 0xF2 or 0xF3 prefix. `PS` is our marker for that.
> Done, but is there a way I should be testing this?
You'd need to make sure it didn't disassemble with 0xf2 or 0xf3 before the regular instruction, but we're pretty lax on testing those cases for other instructions so it's not a big deal.
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https://reviews.llvm.org/D128934/new/
https://reviews.llvm.org/D128934
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