[PATCH] D128886: [RISCV] Add scheduling resources for vector segment instructions.

[Monk Chiang via Phabricator via llvm-commits]

monkchiang updated this revision to Diff 441561.
monkchiang added a comment.

Address comment:

1. Remove ReadVLDSX from VLSEGSched, VLSEGFFSched.
2. Add index vector register read for indexed segment load/store.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128886/new/

https://reviews.llvm.org/D128886

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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