[PATCH] D128886: [RISCV] Add scheduling resources for vector segment instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:120
+class VLSEGSched<int nf, int eew> : Sched<[
+  !cast<SchedReadWrite>("WriteVLSEG" #nf #"e" #eew), ReadVLDX, ReadVLDSX,
+  ReadVMask]>;
----------------
Are there too many reads here? Isn't ReadVLDSX for a stride operand that doesn't exist on unit stride?


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:137
+class VLUXSEGSched<int nf, int eew> : Sched<[
+  !cast<SchedReadWrite>("WriteVLUXSEG" #nf #"e" #eew), ReadVLDX, ReadVLDSX,
+  ReadVMask]>;
----------------
Isn't ReadVLDSX supposed to be read of the stride, but this is an index load. So we need an index vector register read I think.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128886/new/

https://reviews.llvm.org/D128886