[llvm] dbe4bb7 - [PhaseOrdering] add test to show missing folds from PR56119; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2022-06-30T15:51:39-04:00
New Revision: dbe4bb7d12dced75aa54e7942410bed7a8b923ef

URL: https://github.com/llvm/llvm-project/commit/dbe4bb7d12dced75aa54e7942410bed7a8b923ef
DIFF: https://github.com/llvm/llvm-project/commit/dbe4bb7d12dced75aa54e7942410bed7a8b923ef.diff

LOG: [PhaseOrdering] add test to show missing folds from PR56119; NFC

issue #56119

Added: 
    

Modified: 
    llvm/test/Transforms/PhaseOrdering/cmp-logic.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll b/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
index c9532408a2f93..ee64afddbfdf3 100644
--- a/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
+++ b/llvm/test/Transforms/PhaseOrdering/cmp-logic.ll
@@ -1,5 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes='default<O1>' -S < %s | FileCheck %s
+; RUN: opt -passes='default<O1>' -S < %s | FileCheck %s --check-prefixes=CHECK,O1
+; RUN: opt -passes='default<Oz>' -S < %s | FileCheck %s --check-prefixes=CHECK,OZ
+
+target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+
+%struct.a = type { i32 }
 
 define i32 @PR38781(i32 noundef %a, i32 noundef %b) {
 ; CHECK-LABEL: @PR38781(
@@ -97,3 +102,62 @@ lor.end:
   %t0 = phi i1 [ true, %entry ], [ %cmp6, %lor.rhs ]
   ret i1 %t0
 }
+
+ at c = global i32 0, align 4
+
+declare void @foo(...) #3
+
+define i32 @PR56119(i32 %e.coerce) {
+; O1-LABEL: @PR56119(
+; O1-NEXT:  entry:
+; O1-NEXT:    [[CONV2:%.*]] = and i32 [[E_COERCE:%.*]], 255
+; O1-NEXT:    [[REM:%.*]] = urem i32 [[CONV2]], 255
+; O1-NEXT:    [[CMP:%.*]] = icmp eq i32 [[REM]], 7
+; O1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; O1:       if.then:
+; O1-NEXT:    call void (...) @foo()
+; O1-NEXT:    br label [[IF_END]]
+; O1:       if.end:
+; O1-NEXT:    [[TMP0:%.*]] = load i32, ptr @c, align 4
+; O1-NEXT:    ret i32 [[TMP0]]
+;
+; OZ-LABEL: @PR56119(
+; OZ-NEXT:  entry:
+; OZ-NEXT:    [[E_COERCE_FR:%.*]] = freeze i32 [[E_COERCE:%.*]]
+; OZ-NEXT:    [[REM_LHS_TRUNC:%.*]] = trunc i32 [[E_COERCE_FR]] to i8
+; OZ-NEXT:    [[DOTNOT:%.*]] = icmp ne i8 [[REM_LHS_TRUNC]], -1
+; OZ-NEXT:    [[E_COERCE_FR_OP:%.*]] = and i32 [[E_COERCE_FR]], 255
+; OZ-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[E_COERCE_FR_OP]], 7
+; OZ-NEXT:    [[CMP:%.*]] = and i1 [[DOTNOT]], [[CMP2]]
+; OZ-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
+; OZ:       if.then:
+; OZ-NEXT:    tail call void (...) @foo()
+; OZ-NEXT:    br label [[IF_END]]
+; OZ:       if.end:
+; OZ-NEXT:    [[TMP0:%.*]] = load i32, ptr @c, align 4
+; OZ-NEXT:    ret i32 [[TMP0]]
+;
+entry:
+  %e = alloca %struct.a, align 4
+  %coerce.dive = getelementptr inbounds %struct.a, ptr %e, i32 0, i32 0
+  store i32 %e.coerce, ptr %coerce.dive, align 4
+  %b = getelementptr inbounds %struct.a, ptr %e, i32 0, i32 0
+  %0 = load i32, ptr %b, align 4
+  %conv = trunc i32 %0 to i8
+  %conv1 = trunc i64 -1 to i8
+  %conv2 = zext i8 %conv to i32
+  %conv3 = zext i8 %conv1 to i32
+  %rem = srem i32 %conv2, %conv3
+  %conv4 = trunc i32 %rem to i8
+  %conv5 = sext i8 %conv4 to i32
+  %cmp = icmp eq i32 7, %conv5
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  call void (...) @foo() #5
+  br label %if.end
+
+if.end:
+  %1 = load i32, ptr @c, align 4
+  ret i32 %1
+}