[llvm] e44dcfb - [AMDGPU] add alternate tests for max-offset codegen; NFC
Sanjay Patel via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 30 12:51:48 PDT 2022
Author: Sanjay Patel
Date: 2022-06-30T15:51:39-04:00
New Revision: e44dcfb06eb395e065d20978325801d7a70cdf7a
URL: https://github.com/llvm/llvm-project/commit/e44dcfb06eb395e065d20978325801d7a70cdf7a
DIFF: https://github.com/llvm/llvm-project/commit/e44dcfb06eb395e065d20978325801d7a70cdf7a.diff
LOG: [AMDGPU] add alternate tests for max-offset codegen; NFC
As discussed in D128123, the existing test shows a possible
regression when converting sub to xor. This adds tests that
avoid that pattern but still has a offset near 65535. Also,
add a test with the canonical IR for the existing test to show
if the transform is happening with the expected pattern in IR.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
index 8acdc649f2efd..f4ce432e8d677 100644
--- a/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
+++ b/llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll
@@ -105,8 +105,136 @@ entry:
ret void
}
-define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
-; CI-LABEL: add_x_shl_neg_to_sub_max_offset:
+define amdgpu_kernel void @write_ds_sub_max_offset_global_clamp_bit(float %dummy.val) #0 {
+; CI-LABEL: write_ds_sub_max_offset_global_clamp_bit:
+; CI: ; %bb.0:
+; CI-NEXT: s_load_dword s0, s[0:1], 0x0
+; CI-NEXT: s_mov_b64 vcc, 0
+; CI-NEXT: v_not_b32_e32 v0, v0
+; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; CI-NEXT: v_mov_b32_e32 v2, 0x7b
+; CI-NEXT: s_waitcnt lgkmcnt(0)
+; CI-NEXT: v_mov_b32_e32 v1, s0
+; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1
+; CI-NEXT: s_mov_b32 s0, 0
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: s_mov_b32 s3, 0xf000
+; CI-NEXT: s_mov_b32 s2, -1
+; CI-NEXT: s_mov_b32 s1, s0
+; CI-NEXT: ds_write_b32 v0, v2 offset:65532
+; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; CI-NEXT: s_waitcnt vmcnt(0)
+; CI-NEXT: s_endpgm
+;
+; GFX9-LABEL: write_ds_sub_max_offset_global_clamp_bit:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: s_load_dword s0, s[0:1], 0x0
+; GFX9-NEXT: s_mov_b64 vcc, 0
+; GFX9-NEXT: v_not_b32_e32 v0, v0
+; GFX9-NEXT: v_lshlrev_b32_e32 v3, 2, v0
+; GFX9-NEXT: v_mov_b32_e32 v4, 0x7b
+; GFX9-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1
+; GFX9-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-NEXT: ds_write_b32 v3, v4 offset:65532
+; GFX9-NEXT: global_store_dword v[0:1], v2, off
+; GFX9-NEXT: s_waitcnt vmcnt(0)
+; GFX9-NEXT: s_endpgm
+;
+; GFX10-LABEL: write_ds_sub_max_offset_global_clamp_bit:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_load_dword s0, s[0:1], 0x0
+; GFX10-NEXT: v_not_b32_e32 v0, v0
+; GFX10-NEXT: s_mov_b32 vcc_lo, 0
+; GFX10-NEXT: v_mov_b32_e32 v3, 0x7b
+; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v0
+; GFX10-NEXT: v_mov_b32_e32 v0, 0
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: ds_write_b32 v2, v3 offset:65532
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_fmas_f32 v4, s0, s0, s0
+; GFX10-NEXT: global_store_dword v[0:1], v4, off
+; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT: s_endpgm
+ %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
+ %sub1 = sub i32 -1, %x.i
+ %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
+ %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 16383
+ store i32 123, i32 addrspace(3)* %arrayidx
+ %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
+ store volatile float %fmas, float addrspace(1)* null
+ ret void
+}
+
+define amdgpu_kernel void @add_x_shl_max_offset() #1 {
+; CI-LABEL: add_x_shl_max_offset:
+; CI: ; %bb.0:
+; CI-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; CI-NEXT: v_mov_b32_e32 v1, 13
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_write_b8 v0, v1 offset:65535
+; CI-NEXT: s_endpgm
+;
+; GFX9-LABEL: add_x_shl_max_offset:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 13
+; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535
+; GFX9-NEXT: s_endpgm
+;
+; GFX10-LABEL: add_x_shl_max_offset:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 4, v0
+; GFX10-NEXT: v_mov_b32_e32 v1, 13
+; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535
+; GFX10-NEXT: s_endpgm
+ %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %shl = shl i32 %x.i, 4
+ %add = add i32 %shl, 65535
+ %z = zext i32 %add to i64
+ %ptr = inttoptr i64 %z to i8 addrspace(3)*
+ store i8 13, i8 addrspace(3)* %ptr, align 1
+ ret void
+}
+
+define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_alt() #1 {
+; CI-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
+; CI: ; %bb.0:
+; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0
+; CI-NEXT: v_mov_b32_e32 v1, 13
+; CI-NEXT: s_mov_b32 m0, -1
+; CI-NEXT: ds_write_b8 v0, v1 offset:65535
+; CI-NEXT: s_endpgm
+;
+; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
+; GFX9: ; %bb.0:
+; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
+; GFX9-NEXT: v_mov_b32_e32 v1, 13
+; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535
+; GFX9-NEXT: s_endpgm
+;
+; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_alt:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
+; GFX10-NEXT: v_mov_b32_e32 v1, 13
+; GFX10-NEXT: v_sub_nc_u32_e32 v0, 0, v0
+; GFX10-NEXT: ds_write_b8 v0, v1 offset:65535
+; GFX10-NEXT: s_endpgm
+ %x.i = tail call i32 @llvm.amdgcn.workitem.id.x()
+ %.neg = mul i32 %x.i, -4
+ %add = add i32 %.neg, 65535
+ %z = zext i32 %add to i64
+ %ptr = inttoptr i64 %z to i8 addrspace(3)*
+ store i8 13, i8 addrspace(3)* %ptr, align 1
+ ret void
+}
+
+define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset_not_canonical() #1 {
+; CI-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:
; CI: ; %bb.0:
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0
@@ -115,7 +243,7 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
; CI-NEXT: ds_write_b8 v0, v1 offset:65535
; CI-NEXT: s_endpgm
;
-; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset:
+; GFX9-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
@@ -123,7 +251,7 @@ define amdgpu_kernel void @add_x_shl_neg_to_sub_max_offset() #1 {
; GFX9-NEXT: ds_write_b8 v0, v1 offset:65535
; GFX9-NEXT: s_endpgm
;
-; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset:
+; GFX10-LABEL: add_x_shl_neg_to_sub_max_offset_not_canonical:
; GFX10: ; %bb.0:
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v1, 13
More information about the llvm-commits
mailing list