[PATCH] D128631: [AArch64] Initial sched model for Neoverse N2

Thu Jun 30 09:23:17 PDT 2022

dmgreen added a comment.

> Done. For SVE I used the objdump output from the MC tests, removed the duplicates and sorted on opcode. There's still probably a few duplicate variants but the coverage should be good.

Thanks, that's great.

>> I think we can use this new schedule for all "Arm-v9" cores in AArch64.td (that are not in-order). It will almost certainly be a better fit than the older A57 model, and be good to get some decent SVE information.
>
> Sounds good, my only concern is we're quite keen to get this into LLVM 15 which branches around the middle of July I believe and making this the default for all v9 cores presumably raises the bar in terms of validating it is better than the A57 for the v9 cores?

I think for Cortex-A710 we can change it, they are very similar microarchitectures. The performance checks I've ran seem just fine for them. I would change the Cortex-X2 and NeoverseV1 as well, although the core is a little different it would be a shame to leave them off. Neoverse512TVB I know less about, but as it doesn't relate to any specific core I would say a model with SVE scheduling is better than one without. We would presumably add all new cores with the new schedule as opposed to the A57 model, and I would prefer not to leave the other SVE cores behind in that regard.

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Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-basic-instructions.s:1858
+# CHECK-NEXT:  1      2     0.50                        umnegl	x11, w13, w17
+# CHECK-NEXT:  1      1     0.25                        extr	w3, w5, w7, #0
+# CHECK-NEXT:  1      1     0.25                        extr	w11, w13, w17, #31
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Is this missing?

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Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s:4194
+uqincw	x0, #20
+uqincw	x0, #21
+uqincw	x0, #22
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Perhaps try and remove some of these.

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Comment at: llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s:4465
+whilels	p15.d, x0, xzr
+whilels	p15.h, w0, wzr
+whilels	p15.h, x0, xzr
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We can probably get away without different conditions. I don't think they should be important for scheduling.

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  https://reviews.llvm.org/D128631/new/

https://reviews.llvm.org/D128631