[PATCH] D128836: [AMDGPU][GlobalISel] Support register offsets for SMRDs.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Should add some selector MIR tests



================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp:3833
   // SGPR offset is unsigned.
-  if (!GEPInfo.Imm || GEPInfo.Imm < 0 || !isUInt<32>(GEPInfo.Imm))
-    return None;
+  if (AddrInfo[0].SgprParts.size() == 1 && GEPInfo.Imm > 0 &&
+      isUInt<32>(GEPInfo.Imm)) {
----------------
kosarev wrote:
> arsenm wrote:
> > Isn't GEPInfo.Imm > 0 redundant with isUInt<32>?
> I believe `isUInt<32>()` allows zero?
Clearer to change to != 0 then


Repository:
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  https://reviews.llvm.org/D128836/new/

https://reviews.llvm.org/D128836