[PATCH] D128876: [RISCV] Fix wrong register rename for store value during make-compressible optimization

[Kito Cheng via Phabricator via llvm-commits]

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Current implementation will rename both register in store instructions if
we store base address into memory with same base register, it's OK if
the offset is 0, however that is wrong transform if offset isn't 0, give
a smalle example here:

sd      a0, 808(a0)

We should not transform into:

addi    a2, a0, 768
sd      a2, 40(a2)

That should just rename base address like this:

addi    a2, a0, 768
sd      a0, 40(a2)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128876

Files:
  llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp
  llvm/test/CodeGen/RISCV/make-compressible-for-store-address.mir

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