[PATCH] D128006: [RISCV] Avoid changing etype for splat of 0 or -1

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Fraser reported another problem with this patch to me privately.  In addition to the wrong number of bits being written Craig found, we could also construct illegal instruction encodings.  This could happen because we changed the VLMUL of the splat, but did not change the LMUL on the pseudo itself.  As a result, the register allocator would assign e.g. an LMUL1 register, when the VSETVLI was now e.g. LMUL2.  Given only have of registers are legal operands at LMUL2, this has a high chance of producing an illegal instruction encoding.


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  https://reviews.llvm.org/D128006/new/

https://reviews.llvm.org/D128006