[PATCH] D128006: [RISCV] Avoid changing etype for splat of 0 or -1

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll:1571
+; LMULMAX1-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
 ; LMULMAX1-NEXT:    vmv.v.i v8, 0
 ; LMULMAX1-NEXT:    vse32.v v8, (sp)
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craig.topper wrote:
> craig.topper wrote:
> > I don't think this patch is correct. In the old code we zeroed the entire register because lmul was 1. Now we're only zeroing a quarter of the register because lmul is 1/4. The VL in bytes the comment in the code mentions is more or less LMUL.
> Ignore that part of LMUL being VL in bytes. It's really more like LMUL is the upper bound on how much of the register can be updated. If AVL is X0 then you would need the LMUL to be the same independent of SEW. For other AVLs its more complicated.
I agree, this is definitely wrong.  Revert in progress now.

Looking at this again, the whole logic is wrong.  This depends on VLInBytes, not VLMAX.  I don't know what I was thinking here.  


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128006/new/

https://reviews.llvm.org/D128006