[PATCH] D128631: [AArch64] Initial sched model for Neoverse N2

Wed Jun 29 01:47:56 PDT 2022

c-rhodes added subscribers: yutsumi, kawashima-fj.
c-rhodes added a comment.

In D128631#3615625 <https://reviews.llvm.org/D128631#3615625>, @tschuett wrote:

> Could you add something modern to the basic instruction test, like, e.g., MEMTAG and BTI?

BTI is just an alias of HINT, but I've added tests for MTE based on llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt.

================
Comment at: llvm/lib/Target/AArch64/AArch64SchedA64FX.td:21
   let PostRAScheduler       =   1; // Using PostRA sched.
-  let CompleteModel         =   1;
+  let CompleteModel         =   0;

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Matt wrote:
> Is the change to CompleteModel intentional in this patch?
> Is the change to CompleteModel intentional in this patch?

It is, thanks for pointing it out my intention was to notify Fujitsu engineers when I put the patch up, but I completely forgot.

@kawashima-fj @yutsumi 

The A64FX model is missing info for FTSSEL, FMSB, PFIRST. Also, RDFFR info is set on the pseudo and not the real instruction.

I suspect there's a bug in the scheduling code somewhere since the model was marked as complete, yet these missing instructions weren't detected
until I added them for this model. I can't add the missing info for your model so I've just set it to incomplete, but thought I'd let you know.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128631/new/

https://reviews.llvm.org/D128631