[PATCH] D128741: [RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel.

Tue Jun 28 12:20:28 PDT 2022

craig.topper added a comment.

In D128741#3616395 <https://reviews.llvm.org/D128741#3616395>, @asb wrote:

> In D128741#3616350 <https://reviews.llvm.org/D128741#3616350>, @craig.topper wrote:
>
>> In D128741#3616256 <https://reviews.llvm.org/D128741#3616256>, @reames wrote:
>>
>>> Code is fine, but no tests?
>>
>> I don't have a good way to show the change. The post-isel peephole already cleans this up. This is matching it earlier. I'm trying to remove the post-isel peephole.
>
> So is this patch going to be updated to also remove the peephole? (just checking I'm following the planned staging of changes here!)

We also have custom isel code for (add X, C) used by memory operations where C isn't a simm12 or suitable for addi pair. That code generates an (addi (X, C1 <https://reviews.llvm.org/C1>-LoC), LoC) and relies on the peephole to fold the addi. We need to move that into the SelectRegAddrImm too. Then the peephole can be removed.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128741/new/

https://reviews.llvm.org/D128741