[PATCH] D128741: [RISCV] Fold (add X, [-4096, -2049]) or (add X, [2048,4096]) into load/store address during isel.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 28 10:10:25 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: asb, luismarques, reames, jrtc27, frasercrmck.
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Previously we iseled this to a pair of ADDIs and relied on a post
isel peephole to fold one of the ADDIs into the load/store. Now
we split the immediate in two parts the same way isel does and fold
one of the pieces. If the add has a non-memory use it will emit
two isels and larger one will CSE with the ADDI we created for the
the memory use.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128741
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1879,6 +1879,26 @@
}
}
+ // Handle ADD with large immediates.
+ if (Addr.getOpcode() == ISD::ADD && isa<ConstantSDNode>(Addr.getOperand(1))) {
+ int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
+ assert(!isInt<12>(CVal) && "simm12 not already handled?");
+
+ if (isInt<12>(CVal / 2) && isInt<12>(CVal - CVal / 2)) {
+ // We can use an ADDI for part of the offset and fold the rest into the
+ // load/store. This mirrors the AddiPair PatFrag in RISCVInstrInfo.td.
+ int64_t Adj = CVal < 0 ? -2048 : 2047;
+ SDLoc DL(Addr);
+ MVT VT = Addr.getSimpleValueType();
+ Base = SDValue(
+ CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
+ CurDAG->getTargetConstant(Adj, DL, VT)),
+ 0);
+ Offset = CurDAG->getTargetConstant(CVal - Adj, DL, VT);
+ return true;
+ }
+ }
+
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Subtarget->getXLenVT());
return true;
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