[llvm] c755bf6 - [RISCV] Add test coverage for high known bits for vscale

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-06-28T10:04:05-07:00
New Revision: c755bf658f7de41c2ee1d2be4e8080d3acaadbae

URL: https://github.com/llvm/llvm-project/commit/c755bf658f7de41c2ee1d2be4e8080d3acaadbae
DIFF: https://github.com/llvm/llvm-project/commit/c755bf658f7de41c2ee1d2be4e8080d3acaadbae.diff

LOG: [RISCV] Add test coverage for high known bits for vscale

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
index 27d55aed5ad2..82f671fb110a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll
@@ -106,4 +106,45 @@ define i64 @vscale_select(i32 %x, i32 %y) {
   ret i64 %d
 }
 
+define i64 @vscale_high_bits_zero() nounwind {
+; RV64-LABEL: vscale_high_bits_zero:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    srli a0, a0, 3
+; RV64-NEXT:    ret
+;
+; RV32-LABEL: vscale_high_bits_zero:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    srli a0, a0, 3
+; RV32-NEXT:    li a1, 0
+; RV32-NEXT:    ret
+entry:
+  %0 = call i64 @llvm.vscale.i64()
+  %1 = and i64 %0, 2047
+  ret i64 %1
+}
+
+define i64 @vscale_masked() nounwind {
+; RV64-LABEL: vscale_masked:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:    csrr a0, vlenb
+; RV64-NEXT:    srli a0, a0, 3
+; RV64-NEXT:    andi a0, a0, 510
+; RV64-NEXT:    ret
+;
+; RV32-LABEL: vscale_masked:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:    csrr a0, vlenb
+; RV32-NEXT:    srli a0, a0, 3
+; RV32-NEXT:    andi a0, a0, 510
+; RV32-NEXT:    li a1, 0
+; RV32-NEXT:    ret
+entry:
+  %0 = call i64 @llvm.vscale.i64()
+  %1 = and i64 %0, 511
+  ret i64 %1
+}
+
+
 declare i64 @llvm.vscale.i64()