[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

Dave Green via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 28 00:03:36 PDT 2022

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dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. Then I think this patch LGTM


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