[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:102
+      auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
+      MFI->addToWWMVGPRs(MF, Spill.VGPR);
+
----------------
arsenm wrote:
> Why is anything being added to WWM registers here?
This function picks a new VGPR for FP/BP spilling and the actual spilling happens at emitPrologue/emitEpilogue.
We should add them to WWMVGPRs (renamed from 'LaneVGPRs' after Nicolai's suggestion) that track all whole wave VGPRs and their FIs.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1273
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getWWMVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
arsenm wrote:
> Were WWM registers not reserved? I thought they were
Yes, they are. See `SIRegisterInfo::getReservedRegs`, I added some comments below. 


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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:705
   for (Register Reg : MFI->WWMReservedRegs)
     reserveRegisterTuples(Reserved, Reg);
 
----------------
Reserves WWM Reserved registers accumulated during `SIPreAllocateWWMRegs`.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:715
+  for (auto Reg : MFI->getSGPRSpillVGPRs())
+    reserveRegisterTuples(Reserved, Reg);
 
----------------
Reserves the VGPRs used for SGPR spills, accumulated during `SILowerSGPRSpills`.
We won't have this reserving after D124196 where RA allocates/chooses these VGPRs. 


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192