[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:102
+      auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
+      MFI->addToWWMVGPRs(MF, Spill.VGPR);
+
----------------
Why is anything being added to WWM registers here?


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1273
+  for (MachineBasicBlock &MBB : MF) {
+    for (auto &Reg : MFI->getWWMVGPRs())
+      MBB.addLiveIn(Reg.first);
----------------
Were WWM registers not reserved? I thought they were


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192