[PATCH] D128188: [RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset

[luxufan via Phabricator via llvm-commits]

StephenFan updated this revision to Diff 440110.
StephenFan added a comment.

Add a mir test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128188/new/

https://reviews.llvm.org/D128188

Files:
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
  llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
  llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll

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