[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

[Guozhi Wei via Phabricator via llvm-commits]

Carrot updated this revision to Diff 439907.
Carrot added a comment.

Add mir tests.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124564/new/

https://reviews.llvm.org/D124564

Files:
  llvm/include/llvm/CodeGen/MachineCombinerPattern.h
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/test/CodeGen/AArch64/machine-combiner-subadd.ll
  llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir

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