[PATCH] D124564: [MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

If we add `A - (B + C)` are there any other patterns that would be similarly useful? This seems similar to the existing reassociate logic in the machine combiner, but AArch64InstrInfo::isAssociativeAndCommutative is not very thorough under AArch64. Would the new pattern be best to be marked as CombinerObjective::MustReduceDepth similar to the existing REASSOC patterns?

Can you add some mir tests to test some of the edge cases, especially around flag setting instructions.


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  https://reviews.llvm.org/D124564/new/

https://reviews.llvm.org/D124564