[PATCH] D128286: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8b10ffabae48: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f. (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D128286?vs=438752&id=439423#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128286/new/

https://reviews.llvm.org/D128286

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/zve32-types.ll

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