[PATCH] D128435: [AMDGPU] Fix assertion failure on mad with negative immediate addend

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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Without this, the new test case would fail with:

AMDGPUInstPrinter.cpp:545: void llvm::AMDGPUInstPrinter::printImmediate64(uint64_t, const llvm::MCSubtargetInfo &, llvm::raw_ostream &): Assertion `isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882' failed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128435

Files:
  llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
  llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll


Index: llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
+++ llvm/test/CodeGen/AMDGPU/mad_u64_u32.ll
@@ -89,6 +89,31 @@
   ret float %cast
 }
 
+define amdgpu_ps float @mad_i32_vvi_neg(i32 %a, i32 %b) {
+; GFX9-LABEL: mad_i32_vvi_neg:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffed2979
+; GFX9-NEXT:    v_mov_b32_e32 v3, -1
+; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], v0, v1, v[2:3]
+; GFX9-NEXT:    ; return to shader part epilog
+;
+; GFX10-LABEL: mad_i32_vvi_neg:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    v_mad_u64_u32 v[0:1], null, v0, v1, 0xffffffffffed2979
+; GFX10-NEXT:    ; return to shader part epilog
+;
+; GFX11-LABEL: mad_i32_vvi_neg:
+; GFX11:       ; %bb.0:
+; GFX11-NEXT:    v_mov_b32_e32 v2, v1
+; GFX11-NEXT:    v_mov_b32_e32 v3, v0
+; GFX11-NEXT:    v_mad_u64_u32 v[0:1], null, v3, v2, 0xffffffffffed2979
+; GFX11-NEXT:    ; return to shader part epilog
+  %mul = mul i32 %a, %b
+  %add = add i32 %mul, -1234567
+  %cast = bitcast i32 %add to float
+  ret float %cast
+}
+
 define amdgpu_ps float @mad_i32_vcv(i32 %a, i32 %c) {
 ; GFX9-LABEL: mad_i32_vcv:
 ; GFX9:       ; %bb.0:
Index: llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -541,13 +541,8 @@
   else if (Imm == 0x3fc45f306dc9c882 &&
            STI.getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm])
     O << "0.15915494309189532";
-  else {
-    assert(isUInt<32>(Imm) || Imm == 0x3fc45f306dc9c882);
-
-    // In rare situations, we will have a 32-bit literal in a 64-bit
-    // operand. This is technically allowed for the encoding of s_mov_b64.
-    O << formatHex(static_cast<uint64_t>(Imm));
-  }
+  else
+    O << formatHex(Imm);
 }
 
 void AMDGPUInstPrinter::printBLGP(const MCInst *MI, unsigned OpNo,


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