[PATCH] D128286: [RISCV] Disable <vscale x 1 x *> types with Zve32x or Zve32f.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 21 09:44:07 PDT 2022
craig.topper created this revision.
craig.topper added reviewers: reames, frasercrmck, rogfer01, kito-cheng, arcbbb, fakepaper56.
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According to the vector spec, mf8 is not supported for i8 if ELEN
is 32. Similarily mf4 is not suported for i16/f16 or mf2 for i32/f32.
Since RVVBitsPerBlock is 64 and LMUL is calculated as
((MinNumElements * ElementSize) / RVVBitsPerBlock) this means we
need to disable any type with MinNumElements==1.
For generic IR, these types will now be widened in type legalization.
For RVV intrinsics, we'll probably hit a fatal error somewhere. I plan
to work on disabling the intrinsics in the riscv_vector.h header.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D128286
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -112,6 +112,12 @@
if (Subtarget.hasVInstructions()) {
auto addRegClassForRVV = [this](MVT VT) {
+ // Disable the smallest fractional LMUL types if ELEN is less than
+ // RVVBitsPerBlock.
+ unsigned MinElts = RISCV::RVVBitsPerBlock / Subtarget.getELEN();
+ if (VT.getVectorMinNumElements() < MinElts)
+ return;
+
unsigned Size = VT.getSizeInBits().getKnownMinValue();
const TargetRegisterClass *RC;
if (Size <= RISCV::RVVBitsPerBlock)
@@ -472,6 +478,9 @@
}
for (MVT VT : BoolVecVTs) {
+ if (!isTypeLegal(VT))
+ continue;
+
setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
// Mask VTs are custom-expanded into a series of standard nodes
@@ -519,8 +528,7 @@
}
for (MVT VT : IntVecVTs) {
- if (VT.getVectorElementType() == MVT::i64 &&
- !Subtarget.hasVInstructionsI64())
+ if (!isTypeLegal(VT))
continue;
setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
@@ -704,21 +712,31 @@
}
};
- if (Subtarget.hasVInstructionsF16())
- for (MVT VT : F16VecVTs)
+ if (Subtarget.hasVInstructionsF16()) {
+ for (MVT VT : F16VecVTs) {
+ if (!isTypeLegal(VT))
+ continue;
SetCommonVFPActions(VT);
+ }
+ }
- for (MVT VT : F32VecVTs) {
- if (Subtarget.hasVInstructionsF32())
+ if (Subtarget.hasVInstructionsF32()) {
+ for (MVT VT : F32VecVTs) {
+ if (!isTypeLegal(VT))
+ continue;
SetCommonVFPActions(VT);
- SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs);
+ SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs);
+ }
}
- for (MVT VT : F64VecVTs) {
- if (Subtarget.hasVInstructionsF64())
+ if (Subtarget.hasVInstructionsF64()) {
+ for (MVT VT : F64VecVTs) {
+ if (!isTypeLegal(VT))
+ continue;
SetCommonVFPActions(VT);
- SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs);
- SetCommonVFPExtLoadTruncStoreActions(VT, F32VecVTs);
+ SetCommonVFPExtLoadTruncStoreActions(VT, F16VecVTs);
+ SetCommonVFPExtLoadTruncStoreActions(VT, F32VecVTs);
+ }
}
if (Subtarget.useRVVForFixedLengthVectors()) {
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