[PATCH] D128106: [PowerPC] Add support for G_ADD and G_SUB.

[Kai Nacke via Phabricator via llvm-commits]

Kai updated this revision to Diff 438453.
Kai added a comment.

- Removed test in `ppc-irtranslator.ll`
- Added tests for `i8`, `i16`, `i32`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128106/new/

https://reviews.llvm.org/D128106

Files:
  llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
  llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
  llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll


Index: llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/GlobalISel/ppc-isel-arithmentic.ll
@@ -0,0 +1,65 @@
+; RUN: llc -mtriple ppc64le-linux -global-isel -o - < %s | FileCheck %s -check-prefixes=CHECK,LINUX
+
+; CHECK-LABEL: test_addi8:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i8 @test_addi8(i8 %a, i8 %b) {
+  %res = add i8 %a, %b
+  ret i8 %res
+}
+
+; CHECK-LABEL: test_addi16:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i16 @test_addi16(i16 %a, i16 %b) {
+  %res = add i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_addi32:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i32 @test_addi32(i32 %a, i32 %b) {
+  %res = add i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_addi64:
+; LINUX: add 3, 3, 4
+; LINUX: blr
+define i64 @test_addi64(i64 %a, i64 %b) {
+  %res = add i64 %a, %b
+  ret i64 %res
+}
+
+; CHECK-LABEL: test_subi8:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i8 @test_subi8(i8 %a, i8 %b) {
+  %res = sub i8 %a, %b
+  ret i8 %res
+}
+
+; CHECK-LABEL: test_subi16:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i16 @test_subi16(i16 %a, i16 %b) {
+  %res = sub i16 %a, %b
+  ret i16 %res
+}
+
+; CHECK-LABEL: test_subi32:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i32 @test_subi32(i32 %a, i32 %b) {
+  %res = sub i32 %a, %b
+  ret i32 %res
+}
+
+; CHECK-LABEL: test_subi64:
+; LINUX: sub 3, 3, 4
+; LINUX: blr
+define i64 @test_subi64(i64 %a, i64 %b) {
+  %res = sub i64 %a, %b
+  ret i64 %res
+}
Index: llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
+++ llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
@@ -66,6 +66,9 @@
   unsigned MappingID = DefaultMappingID;
 
   switch (Opc) {
+    // Arithmetic ops.
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
     // Bitwise ops.
   case TargetOpcode::G_AND:
   case TargetOpcode::G_OR:
Index: llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
+++ llvm/lib/Target/PowerPC/GISel/PPCLegalizerInfo.cpp
@@ -27,5 +27,8 @@
   getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
       .legalFor({S64})
       .clampScalar(0, S64, S64);
+  getActionDefinitionsBuilder({G_ADD, G_SUB})
+      .legalFor({S64})
+      .clampScalar(0, S64, S64);
   getLegacyLegalizerInfo().computeTables();
 }


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