[PATCH] D126201: [WIP] Very early work to enable isel of fixed length vector extracts from scalable vectors.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/include/llvm/Target/TargetSelectionDAG.td:272
+def SDTSubVecExtract2 : SDTypeProfile<1, 2, [// subvector extract
+    SDTCisVec<0>, SDTCisVec<1>, SDTCisInt<2>
+]>;
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Allen wrote:
> hi @paulwalker-arm:
>    I'm not familiar with the def, do you mean **SDTCisVec<0>** and **SDTCisInt<2>** have different type, so this is guard with **A.isScalable() != B.isScalable() **? thanks.
Yes, specially `<2>` is the index to extract from which is a scalar integer.


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Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1425
 
+  // Extract fixed length subvector from FP SVE vectors
+  def : Pat<(v2f32 (extract_subvector2 (nxv2f32 ZPR:$Zs), (i64 0))),
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Allen wrote:
> hi, @paulwalker-arm:
>    do you still working on it, may be it need more pattern to match above commented pattten?
I've not done anything since this initial version.  Especially since concluding we can probably use `vector_extract_subvec`.  I can pick this up if you want.  I'm kind of interested anyway as a way to remove the original support code from AArch64ISelDAGToDAG.cpp.


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  https://reviews.llvm.org/D126201/new/

https://reviews.llvm.org/D126201