[PATCH] D128085: [RISCV] Assert initial load/store SEW is the EEW
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 20 07:45:37 PDT 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG820e84e05017: [RISCV] Assert initial load/store SEW is the EEW (authored by reames).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128085/new/
https://reviews.llvm.org/D128085
Files:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -408,6 +408,8 @@
// They instead demand the ratio of the two which is used in computing
// EMUL, but which allows us the flexibility to change SEW and LMUL
// provided we don't change the ratio.
+ // Note: We assume that the instructions initial SEW is the EEW encoded
+ // in the opcode. This is asserted when constructing the VSETVLIInfo.
if (getEEWForLoadStore(MI)) {
Res.SEW = false;
Res.LMUL = false;
@@ -885,6 +887,11 @@
} else {
InstrInfo.setAVLReg(RISCV::NoRegister);
}
+#ifndef NDEBUG
+ if (Optional<unsigned> EEW = getEEWForLoadStore(MI)) {
+ assert(SEW == EEW && "Initial SEW doesn't match expected EEW");
+ }
+#endif
InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
return InstrInfo;
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