[llvm] 820e84e - [RISCV] Assert initial load/store SEW is the EEW

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2022-06-20T07:45:21-07:00
New Revision: 820e84e05017d9c58074422e49dc59e27e1cc346

URL: https://github.com/llvm/llvm-project/commit/820e84e05017d9c58074422e49dc59e27e1cc346
DIFF: https://github.com/llvm/llvm-project/commit/820e84e05017d9c58074422e49dc59e27e1cc346.diff

LOG: [RISCV] Assert initial load/store SEW is the EEW

In D127983, I had flipped from using the computed EEW to using the SEW value pulled from the VSETVLI when checking compatibility. This wasn't intentional, though thankfully it appears to be a non-functional difference. The new code does make a unchecked assumption that the initial SEW operand on the load/store is the EEW. This patch clarifies the assumption, and adds an assert to make sure this remains true.

Differential Revision: https://reviews.llvm.org/D128085

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 5b84bb4e5e256..b6b79cffd884a 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -408,6 +408,8 @@ static DemandedFields getDemanded(const MachineInstr &MI) {
   // They instead demand the ratio of the two which is used in computing
   // EMUL, but which allows us the flexibility to change SEW and LMUL
   // provided we don't change the ratio.
+  // Note: We assume that the instructions initial SEW is the EEW encoded
+  // in the opcode.  This is asserted when constructing the VSETVLIInfo.
   if (getEEWForLoadStore(MI)) {
     Res.SEW = false;
     Res.LMUL = false;
@@ -885,6 +887,11 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
   } else {
     InstrInfo.setAVLReg(RISCV::NoRegister);
   }
+#ifndef NDEBUG
+  if (Optional<unsigned> EEW = getEEWForLoadStore(MI)) {
+    assert(SEW == EEW && "Initial SEW doesn't match expected EEW");
+  }
+#endif
   InstrInfo.setVTYPE(VLMul, SEW, TailAgnostic, MaskAgnostic);
 
   return InstrInfo;