[llvm] 621f58e - [Target, CodeGen] Use isImm(), isReg(), etc (NFC)
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 18 07:41:10 PDT 2022
Author: Kazu Hirata
Date: 2022-06-18T07:41:04-07:00
New Revision: 621f58e7161923891c849de89a65fea9f75991bc
URL: https://github.com/llvm/llvm-project/commit/621f58e7161923891c849de89a65fea9f75991bc
DIFF: https://github.com/llvm/llvm-project/commit/621f58e7161923891c849de89a65fea9f75991bc.diff
LOG: [Target, CodeGen] Use isImm(), isReg(), etc (NFC)
Added:
Modified:
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Mips/MipsAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
llvm/lib/Target/X86/X86AsmPrinter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index cb6698c12d8ee..acc4c9a24c012 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -588,8 +588,7 @@ class MachineInstr
/// Return true if operand \p OpIdx is a subregister index.
bool isOperandSubregIdx(unsigned OpIdx) const {
- assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&
- "Expected MO_Immediate operand type.");
+ assert(getOperand(OpIdx).isImm() && "Expected MO_Immediate operand type.");
if (isExtractSubreg() && OpIdx == 2)
return true;
if (isInsertSubreg() && OpIdx == 3)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index e73118aadfc8b..80ba7b5f0d2e7 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -582,7 +582,7 @@ std::string ARMBaseInstrInfo::createMIROperandComment(
return GenericComment;
// If not, check if we have an immediate operand.
- if (Op.getType() != MachineOperand::MO_Immediate)
+ if (!Op.isImm())
return std::string();
// And print its corresponding condition code if the immediate is a
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 0e2335d1611fc..c8e6276aa4de0 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -159,7 +159,7 @@ bool HexagonInstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
auto Op = MI.getOperand(1);
// If the instruction has a global address as operand, it is not cheap
// since the operand will be constant extended.
- if (Op.getType() == MachineOperand::MO_GlobalAddress)
+ if (Op.isGlobal())
return false;
// If the instruction has an operand of size > 16bits, its will be
// const-extended and hence, it is not cheap.
diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
index 7f00478efb86e..9330a791a7cc6 100644
--- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
+++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -522,27 +522,27 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
// See if this is a generic print operand
return AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O);
case 'X': // hex const int
- if ((MO.getType()) != MachineOperand::MO_Immediate)
+ if (!MO.isImm())
return true;
O << "0x" << Twine::utohexstr(MO.getImm());
return false;
case 'x': // hex const int (low 16 bits)
- if ((MO.getType()) != MachineOperand::MO_Immediate)
+ if (!MO.isImm())
return true;
O << "0x" << Twine::utohexstr(MO.getImm() & 0xffff);
return false;
case 'd': // decimal const int
- if ((MO.getType()) != MachineOperand::MO_Immediate)
+ if (!MO.isImm())
return true;
O << MO.getImm();
return false;
case 'm': // decimal const int minus 1
- if ((MO.getType()) != MachineOperand::MO_Immediate)
+ if (!MO.isImm())
return true;
O << MO.getImm() - 1;
return false;
case 'y': // exact log2
- if ((MO.getType()) != MachineOperand::MO_Immediate)
+ if (!MO.isImm())
return true;
if (!isPowerOf2_64(MO.getImm()))
return true;
@@ -550,7 +550,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return false;
case 'z':
// $0 if zero, regular printing otherwise
- if (MO.getType() == MachineOperand::MO_Immediate && MO.getImm() == 0) {
+ if (MO.isImm() && MO.getImm() == 0) {
O << "$0";
return false;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index edfab04adde33..3f9e9dfc2fb73 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1359,7 +1359,7 @@ std::string RISCVInstrInfo::createMIROperandComment(
return GenericComment;
// If not, we must have an immediate operand.
- if (Op.getType() != MachineOperand::MO_Immediate)
+ if (!Op.isImm())
return std::string();
std::string Comment;
diff --git a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
index 3e3dfaa53505e..20bf870c697dc 100644
--- a/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMergeBaseOffset.cpp
@@ -93,7 +93,7 @@ bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
MachineInstr *&LoADDI) {
if (HiLUI.getOpcode() != RISCV::LUI ||
HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI ||
- HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress ||
+ !HiLUI.getOperand(1).isGlobal() ||
HiLUI.getOperand(1).getOffset() != 0 ||
!MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
return false;
@@ -101,7 +101,7 @@ bool RISCVMergeBaseOffsetOpt::detectLuiAddiGlobal(MachineInstr &HiLUI,
LoADDI = &*MRI->use_instr_begin(HiLuiDestReg);
if (LoADDI->getOpcode() != RISCV::ADDI ||
LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO ||
- LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress ||
+ !LoADDI->getOperand(2).isGlobal() ||
LoADDI->getOperand(2).getOffset() != 0 ||
!MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
return false;
diff --git a/llvm/lib/Target/X86/X86AsmPrinter.cpp b/llvm/lib/Target/X86/X86AsmPrinter.cpp
index 6e702730e8ea4..c205395aa0849 100644
--- a/llvm/lib/Target/X86/X86AsmPrinter.cpp
+++ b/llvm/lib/Target/X86/X86AsmPrinter.cpp
@@ -249,7 +249,7 @@ void X86AsmPrinter::PrintOperand(const MachineInstr *MI, unsigned OpNo,
void X86AsmPrinter::PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (!Modifier || MO.getType() != MachineOperand::MO_Register)
+ if (!Modifier || !MO.isReg())
return PrintOperand(MI, OpNo, O);
if (MI->getInlineAsmDialect() == InlineAsm::AD_ATT)
O << '%';
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