[PATCH] D118300: [Spill2Reg][3/9] Code generation part 1.

[Vasileios Porpodas via Phabricator via llvm-commits]

vporpo marked an inline comment as done.
vporpo added inline comments.


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Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:2029
+  virtual const TargetRegisterClass *
+  getVectorRegisterClassForSpill2Reg(const TargetRegisterInfo *TRI) const {
+    llvm_unreachable(
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Carrot wrote:
> For different sized registers we may spill to different vector register class. For example on ARM with NEON, 32 bit value can be spilled to S registers, 64 bit value can be spilled to D registers.
I added an additional argument to this function to pass the hard register being spilled, such that each target can decide which vector register class to use.


Repository:
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  https://reviews.llvm.org/D118300/new/

https://reviews.llvm.org/D118300