[PATCH] D118300: [Spill2Reg][3/9] Code generation part 1.
Guozhi Wei via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 17 11:36:50 PDT 2022
Carrot added inline comments.
================
Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:2029
+ virtual const TargetRegisterClass *
+ getVectorRegisterClassForSpill2Reg(const TargetRegisterInfo *TRI) const {
+ llvm_unreachable(
----------------
For different sized registers we may spill to different vector register class. For example on ARM with NEON, 32 bit value can be spilled to S registers, 64 bit value can be spilled to D registers.
================
Comment at: llvm/include/llvm/CodeGen/TargetInstrInfo.h:2032
+ "Target didn't implement "
+ "TargetInstrInfo::createVirtualVectorRegisterForSpillToReg()");
+ }
----------------
Other functions use ! instead of ().
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D118300/new/
https://reviews.llvm.org/D118300
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