[llvm] cbf6737 - [RISCV] Use RVVBitsPerBlock instead of hardcoding multiples of 64. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-06-17T14:10:39-07:00
New Revision: cbf6737cc40245dd14e0fc96779f02a64531e2bc

URL: https://github.com/llvm/llvm-project/commit/cbf6737cc40245dd14e0fc96779f02a64531e2bc
DIFF: https://github.com/llvm/llvm-project/commit/cbf6737cc40245dd14e0fc96779f02a64531e2bc.diff

LOG: [RISCV] Use RVVBitsPerBlock instead of hardcoding multiples of 64. NFC

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index ffab969ec33f..75f144742c71 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -113,16 +113,17 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   if (Subtarget.hasVInstructions()) {
     auto addRegClassForRVV = [this](MVT VT) {
       unsigned Size = VT.getSizeInBits().getKnownMinValue();
-      assert(Size <= 512 && isPowerOf2_32(Size));
       const TargetRegisterClass *RC;
-      if (Size <= 64)
+      if (Size <= RISCV::RVVBitsPerBlock)
         RC = &RISCV::VRRegClass;
-      else if (Size == 128)
+      else if (Size == 2 * RISCV::RVVBitsPerBlock)
         RC = &RISCV::VRM2RegClass;
-      else if (Size == 256)
+      else if (Size == 4 * RISCV::RVVBitsPerBlock)
         RC = &RISCV::VRM4RegClass;
-      else
+      else if (Size == 8 * RISCV::RVVBitsPerBlock)
         RC = &RISCV::VRM8RegClass;
+      else
+        llvm_unreachable("Unexpected size");
 
       addRegisterClass(VT, RC);
     };