[llvm] deb7655 - [PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and MFVSCR as not swappable.

[Quinn Pham via llvm-commits]

Author: Quinn Pham
Date: 2022-06-17T10:14:24-05:00
New Revision: deb7655209a7d74257b651ade97bfc63043174ec

URL: https://github.com/llvm/llvm-project/commit/deb7655209a7d74257b651ade97bfc63043174ec
DIFF: https://github.com/llvm/llvm-project/commit/deb7655209a7d74257b651ade97bfc63043174ec.diff

LOG: [PowerPC] Fix PPCVSXSwapRemoval pass to include MTVSCR and MFVSCR as not swappable.

This patch adds the instructions `MTVSCR` and `MFVSCR` as not swappable to the
PPCVSXSwapRemoval pass because they are not lane-insensitive. This will prevent
the compiler from optimizing out required swaps when using `lxvd2x` and
`stxvd2x`.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D128062

Added: 
    llvm/test/CodeGen/PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
index ff251f55afff9..04fc7667257e0 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
@@ -519,6 +519,8 @@ bool PPCVSXSwapRemoval::gatherVectorInstructions() {
       case PPC::XXSLDWI:
       case PPC::XSCVDPSPN:
       case PPC::XSCVSPDPN:
+      case PPC::MTVSCR:
+      case PPC::MFVSCR:
         break;
       }
     }

diff  --git a/llvm/test/CodeGen/PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll b/llvm/test/CodeGen/PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll
new file mode 100644
index 0000000000000..604afe0848251
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/mtvsrc-mfvscr-PPCVSXSwapRemoval.ll
@@ -0,0 +1,37 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
+; RUN:   -mcpu=pwr8 -O2 < %s | FileCheck %s
+
+define void @test_mtvscr() {
+; CHECK-LABEL: test_mtvscr:
+; CHECK:       # %bb.0: # %test_mtvscr_entry
+; CHECK-NEXT:    addi 3, 1, -16
+; CHECK-NEXT:    lxvd2x 0, 0, 3
+; CHECK-NEXT:    xxswapd 34, 0
+; CHECK-NEXT:    mtvscr 2
+; CHECK-NEXT:    blr
+test_mtvscr_entry:
+  %0 = alloca <4 x i32>
+  %1 = load <4 x i32>, <4 x i32>* %0
+  call void @llvm.ppc.altivec.mtvscr(<4 x i32> %1)
+  ret void
+}
+
+define void @test_mfvscr() {
+; CHECK-LABEL: test_mfvscr:
+; CHECK:       # %bb.0: # %test_mfvscr_entry
+; CHECK-NEXT:    mfvscr 2
+; CHECK-NEXT:    addi 3, 1, -16
+; CHECK-NEXT:    xxswapd 0, 34
+; CHECK-NEXT:    stxvd2x 0, 0, 3
+; CHECK-NEXT:    blr
+test_mfvscr_entry:
+  %0 = alloca <8 x i16>
+  %1 = call <8 x i16> @llvm.ppc.altivec.mfvscr()
+  store <8 x i16> %1, <8 x i16>* %0
+  ret void
+}
+
+declare void @llvm.ppc.altivec.mtvscr(<4 x i32>)
+
+declare <8 x i16> @llvm.ppc.altivec.mfvscr()