[PATCH] D128016: Recommit "[RISCV] Enable subregister liveness tracking for RVV."

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:206
+    return EnableSubRegLiveness;
+  // Enable subregister liveness for RVV to better handle LMUL>1 and segment
+  // load/store.
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reames wrote:
> Is there an active reason not to enable sub-reg liveness unconditionally?
I wasn't sure if there was any compile time or memory usage impact from it that we could avoid when it wasn't needed. Last I checked ARM only enabled when MVE was enabled so I thought maybe there was some reason.


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  https://reviews.llvm.org/D128016/new/

https://reviews.llvm.org/D128016