[PATCH] D127996: [RISCV] Delete dead elideCopy code in InsertVSETVLI [nfc]
Philip Reames via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 16 11:26:55 PDT 2022
reames created this revision.
reames added reviewers: craig.topper, frasercrmck, kito-cheng.
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This code appears to be dead. A simple whole register copy of an IMPLICIT_DEF, is simply an IMPLICIT_DEF of it's own. (This would not be true for freeze, but is for copy.)
If we find a case which gets here with vector operand copy of an IMPLICIT_DEF, we most likely have an earlier missed optimization anyways.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D127996
Files:
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
Index: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -780,19 +780,6 @@
return RISCV::X0 == MI.getOperand(0).getReg();
}
-static MachineInstr *elideCopies(MachineInstr *MI,
- const MachineRegisterInfo *MRI) {
- while (true) {
- if (!MI->isFullCopy())
- return MI;
- if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
- return nullptr;
- MI = MRI->getVRegDef(MI->getOperand(1).getReg());
- if (!MI)
- return nullptr;
- }
-}
-
static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags,
const MachineRegisterInfo *MRI) {
VSETVLIInfo InstrInfo;
@@ -828,13 +815,10 @@
// If the tied operand is an IMPLICIT_DEF we can keep TailAgnostic.
const MachineOperand &UseMO = MI.getOperand(UseOpIdx);
MachineInstr *UseMI = MRI->getVRegDef(UseMO.getReg());
- if (UseMI) {
- UseMI = elideCopies(UseMI, MRI);
- if (UseMI && UseMI->isImplicitDef()) {
- TailAgnostic = true;
- if (UsesMaskPolicy)
- MaskAgnostic = true;
- }
+ if (UseMI && UseMI->isImplicitDef()) {
+ TailAgnostic = true;
+ if (UsesMaskPolicy)
+ MaskAgnostic = true;
}
// Some pseudo instructions force a tail agnostic policy despite having a
// tied def.
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