[PATCH] D127983: [RISCV] Start merging demanded reasoning - starting with load/stores [nfc]

[Philip Reames via Phabricator via llvm-commits]

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This change merges the logic for reasoning about demanded portions of the VTYPE register between the main dataflow algorithm and the backwards mutation post pass.  In the process, we get to delete a bunch of now redundant code.

This should be entirely NFC.  I included a slight hack (see TODO) to avoid changing behavior in the post pass while being able to use the generalized logic in the prepass.  I will fix the TODO in a separate change once this lands.

@reviewers - Main reason for posting this for review is for a sanity check on the code added to handle the pre-lowering form.  I think I got that right; the existing forward direction code is basically only ever called on instructions with SEW or explicit vsetvlis.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D127983

Files:
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

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